zynq-rs/libboard_zynq/src
Astro 29bf29a037 add some fpga regs 2020-03-25 13:02:01 +01:00
..
clocks delint 2020-01-30 23:18:14 +01:00
ddr libboard_zynq::clocks: setup clock sources and cpu clock 2020-01-23 23:15:10 +01:00
devc add some fpga regs 2020-03-25 13:02:01 +01:00
dmac libboard_zynq::dmac: enable mod, add channel_regs() 2020-02-03 23:04:26 +01:00
eth libboard_zynq::clocks: setup clock sources and cpu clock 2020-01-23 23:15:10 +01:00
flash delint 2020-01-30 23:18:14 +01:00
uart libboard_zynq::clocks: setup clock sources and cpu clock 2020-01-23 23:15:10 +01:00
axi_gp.rs split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00
axi_hp.rs split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00
lib.rs libboard_zynq::dmac: enable mod, add channel_regs() 2020-02-03 23:04:26 +01:00
mpcore.rs split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00
slcr.rs add some fpga regs 2020-03-25 13:02:01 +01:00
stdio.rs libboard_zynq::stdio: add drop_uart() 2020-01-23 23:14:50 +01:00