forked from M-Labs/zynq-rs
92 lines
2.7 KiB
Rust
92 lines
2.7 KiB
Rust
use libregister::{
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register, register_at,
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register_bit, register_bits
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};
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// With reference to:
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//
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// artiq:artiq/gateware/targets/kasli.py:
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// self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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//
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// misoc:misoc/cores/gpio.py:
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// class GPIOTristate(Module, AutoCSR):
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// def __init__(self, signals, reset_out=0, reset_oe=0):
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// l = len(signals)
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// self._in = CSRStatus(l)
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// self._out = CSRStorage(l, reset=reset_out)
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// self._oe = CSRStorage(l, reset=reset_oe)
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//
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// Hence, using GPIOs as SCL and SDA GPIOs respectively.
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//
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// Current compatibility:
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// zc706: GPIO 50, 51 == SCL, SDA
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pub struct RegisterBlock {
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pub gpio_output_mask: &'static mut GPIOOutputMask,
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pub gpio_input: &'static mut GPIOInput,
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pub gpio_direction: &'static mut GPIODirection,
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pub gpio_output_enable: &'static mut GPIOOutputEnable,
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}
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impl RegisterBlock {
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pub fn i2c() -> Self {
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Self {
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gpio_output_mask: GPIOOutputMask::new(),
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gpio_input: GPIOInput::new(),
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gpio_direction: GPIODirection::new(),
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gpio_output_enable: GPIOOutputEnable::new()
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}
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}
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}
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// MASK_DATA_1_MSW:
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// Maskable output data for MIO[53:48]
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register!(gpio_output_mask, GPIOOutputMask, RW, u32);
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#[cfg(feature = "target_zc706")]
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register_at!(GPIOOutputMask, 0xE000A00C, new);
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// Output for SCL
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_output_mask, scl_o, 2);
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// Output for SDA
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_output_mask, sda_o, 3);
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// Mask for keeping bits except SCL and SDA unchanged
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#[cfg(feature = "target_zc706")]
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register_bits!(gpio_output_mask, mask, u16, 16, 31);
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// DATA_1_RO:
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// Input data for MIO[53:32]
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register!(gpio_input, GPIOInput, RO, u32);
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#[cfg(feature = "target_zc706")]
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register_at!(GPIOInput, 0xE000A064, new);
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// Input for SCL
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_input, scl, 18);
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// Input for SDA
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_input, sda, 19);
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// DIRM_1:
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// Direction mode for MIO[53:32]; 0/1 = in/out
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register!(gpio_direction, GPIODirection, RW, u32);
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#[cfg(feature = "target_zc706")]
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register_at!(GPIODirection, 0xE000A244, new);
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// Direction for SCL
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_direction, scl, 18);
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// Direction for SDA
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_direction, sda, 19);
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// OEN_1:
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// Output enable for MIO[53:32]
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register!(gpio_output_enable, GPIOOutputEnable, RW, u32);
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#[cfg(feature = "target_zc706")]
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register_at!(GPIOOutputEnable, 0xE000A248, new);
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// Output enable for SCL
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_output_enable, scl, 18);
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// Output enable for SDA
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#[cfg(feature = "target_zc706")]
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register_bit!(gpio_output_enable, sda, 19);
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