Bare-metal Rust on Zynq-7000
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Astro 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
2019-11-11 00:06:35 +01:00
.cargo define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
openocd openocd: configure SRST for digilent_jtag_smt2_nc + Zynq 2019-11-05 12:36:07 +08:00
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armv7-none-eabihf.json define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
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shell.nix default.nix: build zc706 2019-09-26 17:54:37 +02:00

README.md

Build

nix-shell --command "cargo xbuild --release"

Debug

Using the Xilinx toolchain

Tested with the ZC706 board.

Run the Xilinx Microprocessor Debugger:

/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64/xmd

Connect to target (given it is connected and you have permissions):

connect arm hw

Leave xmd running.

Start the Xilinx version of the GNU debugger with your latest build:

/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin/arm-xilinx-linux-gnueabi-gdb zc706

Connect the debugger to xmd over TCP on localhost:

target remote :1234

Proceed using gdb with load, c

Using OpenOCD

Running on the ZC706

nix-shell --command "cargo xbuild --release"
cd openocd
openocd -f zc706.cfg

Running on the Cora Z7-10

nix-shell --command "cargo xbuild --release --no-default-features --features=target_cora_z7_10"
cd openocd
openocd -f cora-z7-10.cfg