forked from M-Labs/zynq-rs
380 lines
12 KiB
Rust
380 lines
12 KiB
Rust
use super::{adma::Adma2DescTable, cmd, CardType, CmdTransferError, Sdio};
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use libcortex_a9::cache;
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use libregister::{RegisterR, RegisterRW, RegisterW};
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use log::{trace, debug};
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#[derive(Debug)]
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pub enum CardInitializationError {
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AlreadyInitialized,
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NoCardInserted,
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InitializationFailedOther,
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InitializationFailedCmd(CmdTransferError),
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}
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impl core::fmt::Display for CardInitializationError {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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use CardInitializationError::*;
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write!(f, "Card initialization error: ")?;
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match self {
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AlreadyInitialized => write!(f, "Card already initialized."),
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NoCardInserted => write!(f, "No card inserted, check if the card is inserted properly."),
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InitializationFailedOther => write!(f, "Unknown error. Please check the debug messages."),
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InitializationFailedCmd(x) => write!(f, "{}", x)
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}
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}
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}
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impl From<CmdTransferError> for CardInitializationError {
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fn from(error: CmdTransferError) -> Self {
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CardInitializationError::InitializationFailedCmd(error)
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}
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}
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#[derive(Debug)]
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enum CardVersion {
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SdVer1,
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SdVer2,
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}
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pub struct SdCard {
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sdio: Sdio,
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adma2_desc_table: Adma2DescTable,
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card_version: CardVersion,
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hcs: bool,
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card_id: [u32; 4],
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rel_card_addr: u32,
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sector_cnt: u32,
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switch_1v8: bool,
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width_4_bit: bool,
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}
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const BLK_SIZE_MASK: u16 = 0x00000FFF;
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impl core::fmt::Display for SdCard {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "SdCard: \n card version: {:?}\n hcs: {}\n card id: {:?}\n rel card addr: {}\n sector count: {}",
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self.card_version, self.hcs, self.card_id, self.rel_card_addr, self.sector_cnt)
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}
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}
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impl SdCard {
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fn sd_card_initialize(&mut self) -> Result<(), CardInitializationError> {
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use cmd::{args::*, SdCmd::*};
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if !self.sdio.is_card_inserted() {
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return Err(CardInitializationError::NoCardInserted);
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}
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// CMD0
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self.sdio.cmd_transfer(CMD0, 0, 0)?;
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match self.sdio.cmd_transfer(CMD8, CMD8_VOL_PATTERN, 0) {
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Err(CmdTransferError::CmdTimeout) => {
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// reset
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self.sdio
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.regs
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.clock_control
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.modify(|_, w| w.software_reset_cmd(true));
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// wait until reset is completed
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while self.sdio.regs.clock_control.read().software_reset_cmd() {}
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}
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// for other error, return initialization failed
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Err(e) => return Err(CardInitializationError::from(e)),
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_ => (),
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}
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self.card_version = if self.sdio.regs.responses[0].read() != CMD8_VOL_PATTERN {
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CardVersion::SdVer1
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} else {
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CardVersion::SdVer2
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};
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// send ACMD41 while card is still busy with power up
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loop {
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self.sdio.cmd_transfer(CMD55, 0, 0)?;
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self.sdio
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.cmd_transfer(ACMD41, ACMD41_HCS | ACMD41_3V3 | (0x1FF << 15), 0)?;
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if (self.sdio.regs.responses[0].read() & RESPOCR_READY) != 0 {
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break;
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}
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}
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let response = self.sdio.regs.responses[0].read();
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// update HCS support flag
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self.hcs = (response & ACMD41_HCS) != 0;
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if (response & OCR_S18) != 0 {
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self.switch_1v8 = true;
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self.sdio.switch_voltage()?;
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}
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self.sdio.cmd_transfer(CMD2, 0, 0)?;
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for i in 0..=3 {
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self.card_id[i] = self.sdio.regs.responses[i].read();
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}
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self.rel_card_addr = 0;
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while self.rel_card_addr == 0 {
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self.sdio.cmd_transfer(CMD3, 0, 0)?;
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self.rel_card_addr = self.sdio.regs.responses[0].read() & 0xFFFF0000;
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}
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self.sdio.cmd_transfer(CMD9, self.rel_card_addr, 0)?;
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self.sdio
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.regs
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.interrupt_status
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.modify(|_, w| w.transfer_complete());
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let mut csd: [u32; 4] = [0, 0, 0, 0];
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for i in 0..=3 {
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csd[i] = self.sdio.regs.responses[i].read();
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trace!("CSD[{}] = {:0X}", i, csd[i]);
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}
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const CSD_STRUCT_MSK: u32 = 0x00C00000;
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const C_SIZE_MULT_MASK: u32 = 0x00000380;
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const C_SIZE_LOWER_MASK: u32 = 0xFFC00000;
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const C_SIZE_UPPER_MASK: u32 = 0x00000003;
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const READ_BLK_LEN_MASK: u32 = 0x00000F00;
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const CSD_V2_C_SIZE_MASK: u32 = 0x3FFFFF00;
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const XSDPS_BLK_SIZE_512_MASK: u32 = 0x200;
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if ((csd[3] & CSD_STRUCT_MSK) >> 22) == 0 {
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let blk_len = 1 << ((csd[2] & READ_BLK_LEN_MASK) >> 8);
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let mult = 1 << (((csd[1] & C_SIZE_MULT_MASK) >> 7) + 2);
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let mut device_size = (csd[1] & C_SIZE_LOWER_MASK) >> 22;
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device_size |= (csd[2] & C_SIZE_UPPER_MASK) << 10;
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device_size = (device_size + 1) * mult;
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device_size = device_size * blk_len;
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self.sector_cnt = device_size / XSDPS_BLK_SIZE_512_MASK;
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} else if ((csd[3] & CSD_STRUCT_MSK) >> 22) == 1 {
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self.sector_cnt = (((csd[1] & CSD_V2_C_SIZE_MASK) >> 8) + 1) * 1024;
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} else {
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return Err(CardInitializationError::InitializationFailedOther);
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}
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self.sdio.change_clk_freq(25_000_000);
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// CMD7: select card
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self.sdio.cmd_transfer(CMD7, self.rel_card_addr, 0)?;
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// pull up
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self.sdio.cmd_transfer(CMD55, self.rel_card_addr, 0)?;
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self.sdio.cmd_transfer(ACMD42, 0, 0)?;
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let mut scr: [u8; 32] = [0; 32];
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self.get_bus_width(&mut scr)?;
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trace!("SCR={:?}", scr);
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if scr[1] & 0x4 != 0 {
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// 4bit support
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debug!("4 bit support");
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self.change_bus_width()?;
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}
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self.sdio.set_block_size(512)?;
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Ok(())
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}
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/// Convert Sdio into SdCard struct, error if no card inserted or it is not an SD card.
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pub fn from_sdio(mut sdio: Sdio) -> Result<Self, CardInitializationError> {
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match sdio.identify_card()? {
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CardType::CardSd => (),
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_ => return Err(CardInitializationError::NoCardInserted),
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};
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let mut _self = SdCard {
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sdio,
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adma2_desc_table: Adma2DescTable::new(),
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card_version: CardVersion::SdVer1,
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hcs: false,
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card_id: [0, 0, 0, 0],
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rel_card_addr: 0,
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sector_cnt: 0,
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switch_1v8: false,
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width_4_bit: false,
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};
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_self.sd_card_initialize()?;
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Ok(_self)
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}
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/// Convert SdCard struct back to Sdio struct.
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pub fn to_sdio(self) -> Sdio {
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self.sdio
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}
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/// read blocks starting from an address. Each block has length 512 byte.
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/// Note that the address is block address, i.e. 0 for 0~512, 1 for 512~1024, etc.
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pub fn read_block(
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&mut self,
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address: u32,
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block_cnt: u16,
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buffer: &mut [u8],
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) -> Result<(), CmdTransferError> {
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assert!(buffer.len() >= (block_cnt as usize) * 512);
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// set block size if not set already
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if self
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.sdio
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.regs
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.block_size_block_count
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.read()
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.transfer_block_size()
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!= 512
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{
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self.sdio.set_block_size(512)?;
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}
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let real_addr = if self.hcs {
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address
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} else {
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// standard capacity card uses byte address
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address * 0x200
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};
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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cache::dcci_slice(buffer);
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let cmd = if block_cnt == 1 {
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cmd::SdCmd::CMD17
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} else {
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cmd::SdCmd::CMD18
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};
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let mode = if block_cnt == 1 {
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super::regs::TransferModeCommand::zeroed()
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.block_count_en(true)
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.direction_select(true)
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.dma_en(true)
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} else {
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super::regs::TransferModeCommand::zeroed()
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.auto_cmd12_en(true)
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.block_count_en(true)
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.direction_select(true)
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.multi_block_en(true)
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.dma_en(true)
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};
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self.sdio
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.cmd_transfer_with_mode(cmd, real_addr, block_cnt, mode)?;
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self.wait_transfer_complete()?;
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cache::dcci_slice(buffer);
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Ok(())
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}
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/// write blocks starting from an address. Each block has length 512 byte.
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/// Note that the address is block address, i.e. 0 for 0~512, 1 for 512~1024, etc.
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pub fn write_block(
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&mut self,
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address: u32,
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block_cnt: u16,
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buffer: &[u8],
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) -> Result<(), CmdTransferError> {
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assert!(buffer.len() >= (block_cnt as usize) * 512);
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// set block size if not set already
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if self
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.sdio
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.regs
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.block_size_block_count
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.read()
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.transfer_block_size()
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!= 512
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{
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self.sdio.set_block_size(512)?;
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}
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let real_addr = if self.hcs {
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address
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} else {
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// standard capacity card uses byte address
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address * 0x200
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};
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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cache::dcci_slice(buffer);
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let cmd = if block_cnt == 1 {
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cmd::SdCmd::CMD24
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} else {
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cmd::SdCmd::CMD25
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};
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let mode = if block_cnt == 1 {
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super::regs::TransferModeCommand::zeroed()
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.block_count_en(true)
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.dma_en(true)
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} else {
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super::regs::TransferModeCommand::zeroed()
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.auto_cmd12_en(true)
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.block_count_en(true)
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.multi_block_en(true)
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.dma_en(true)
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};
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self.sdio
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.cmd_transfer_with_mode(cmd, real_addr, block_cnt, mode)?;
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// wait for transfer complete interrupt
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self.wait_transfer_complete()?;
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cache::dcci_slice(buffer);
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Ok(())
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}
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fn get_bus_width(&mut self, buf: &mut [u8]) -> Result<(), CmdTransferError> {
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use cmd::SdCmd::*;
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debug!("Getting bus width");
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for i in 0..8 {
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buf[i] = 0;
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}
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// send block write command
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self.sdio.cmd_transfer(CMD55, self.rel_card_addr, 0)?;
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let blk_cnt: u16 = 1;
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let blk_size: u16 = 8 & BLK_SIZE_MASK;
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self.sdio
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.regs
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.block_size_block_count
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.modify(|_, w| w.transfer_block_size(blk_size));
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self.adma2_desc_table.setup(&mut self.sdio, blk_cnt as u32, buf);
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cache::dcci_slice(buf);
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self.sdio.cmd_transfer_with_mode(
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ACMD51,
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0,
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blk_cnt,
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super::regs::TransferModeCommand::zeroed()
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.dma_en(true)
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.direction_select(true),
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)?;
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self.wait_transfer_complete()?;
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cache::dcci_slice(buf);
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Ok(())
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}
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fn change_bus_width(&mut self) -> Result<(), CmdTransferError> {
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use cmd::SdCmd::*;
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debug!("Changing bus width");
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self.sdio.cmd_transfer(CMD55, self.rel_card_addr, 0)?;
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self.width_4_bit = true;
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self.sdio.cmd_transfer(ACMD6, 0x2, 0)?;
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self.sdio.delay(1);
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self.sdio
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.regs
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.control
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.modify(|_, w| w.data_width_select(true));
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Ok(())
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}
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fn wait_transfer_complete(&mut self) -> Result<(), CmdTransferError> {
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trace!("Wait for transfer complete");
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let mut status = self.sdio.regs.interrupt_status.read();
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while !status.transfer_complete() {
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self.sdio.check_error(&status)?;
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status = self.sdio.regs.interrupt_status.read();
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}
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trace!("Clearing transfer complete");
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self.sdio
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.regs
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.interrupt_status
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.modify(|_, w| w.transfer_complete());
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Ok(())
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}
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}
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