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b2c707d543
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ddr: remove superfluous _reg from register names
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2020-07-03 02:20:10 +02:00 |
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c0e66a632c
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ps7_init: move from experiments to libboard_zynq
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2020-06-25 01:40:42 +02:00 |
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b33ccf83ba
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eth: doc
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2020-06-18 18:07:50 +02:00 |
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a80a2c67ef
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eth: put desc list behind UncachedSlice, invalidate buffers, add barriers
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2020-06-18 01:28:29 +02:00 |
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98f5099684
|
removed newline character
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2020-06-16 17:36:01 +08:00 |
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2c3fa991ad
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implemented display trait for errors
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2020-06-16 17:36:01 +08:00 |
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2c14a2a1a2
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fixed global timer reset
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2020-06-16 17:31:37 +08:00 |
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191da7c959
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Added Copy trait for Milliseconds struct.
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2020-06-16 14:56:29 +08:00 |
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d52466cacf
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DevC driver refactored.
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2020-06-16 14:55:53 +08:00 |
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a17a5d2925
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sdcard: Changed some debug to trace.
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2020-06-15 16:54:30 +08:00 |
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e0f26871db
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devc working!
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2020-06-15 16:07:31 +08:00 |
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82ec1ba7a7
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sdio: better logging
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2020-06-13 16:31:25 +08:00 |
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d3b488bfb3
|
standard capacity support
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2020-06-11 10:21:01 +08:00 |
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074b3547de
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sdio: fix unsound MaybeUninit usage
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2020-06-11 10:07:19 +08:00 |
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316ea61702
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sdio: move ADMA2_DESCR32_TABLE into SdCard
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2020-06-11 10:07:19 +08:00 |
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1586190712
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sdio: turn Adma2Desc32.attribute into a register!
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2020-06-11 10:07:19 +08:00 |
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32349e9dec
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sdio: convert Adma2Desc32 to VolatileCells, make ADMA2_DESCR32_TABLE: MaybeUninit
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2020-06-11 10:07:19 +08:00 |
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b942cdcbc8
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sdio: change Adma2Desc32 alignment from 1 to 4
this should not break anything.
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2020-06-11 10:07:19 +08:00 |
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a1a211334f
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eth: always just allocate desc list + buffers
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
|
2020-06-11 00:21:18 +02:00 |
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cf17a1c60a
|
removed unneeded methods
|
2020-06-10 12:55:22 +08:00 |
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5332587de6
|
Changed mutability
|
2020-06-10 12:54:50 +08:00 |
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0ebc4a61c8
|
Modified SDIO to handle u8 buffer instead of u32.
|
2020-06-09 17:03:17 +08:00 |
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236592ae66
|
SDIO module completed
|
2020-06-05 12:27:12 +08:00 |
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2c82fb793e
|
Merge pull request 'sdio-registers' (#29)
|
2020-05-15 06:44:32 +08:00 |
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0c48dd934e
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libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en
|
2020-05-10 22:14:55 +02:00 |
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3841accd9c
|
libboard_zynq: fix ddr memtest range
|
2020-05-09 02:53:58 +02:00 |
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3e02980c20
|
libboard_zynq: fix access to "full" 1022 MB on target_zc706
|
2020-05-09 02:35:39 +02:00 |
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73b0ec9837
|
fixed typo
|
2020-05-06 13:58:46 +08:00 |
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4acee21c05
|
Merge branch 'master' of git.m-labs.hk:M-Labs/zc706 into sdio-registers
|
2020-05-06 11:06:38 +08:00 |
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ce844f1b02
|
devc: add is_done()
|
2020-05-04 22:16:53 +08:00 |
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c955eaae7f
|
libboard_zynq: flush Uart by waiting for tx idle
|
2020-05-02 23:32:01 +02:00 |
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0f666c570c
|
libboard_zynq: remove unneeded Uart flush
|
2020-05-02 23:30:45 +02:00 |
|
|
244ccdeac2
|
finished register definitions
|
2020-05-01 15:38:07 +08:00 |
|
|
e047c2900b
|
ddr: log clock info with debug level
|
2020-05-01 12:27:43 +08:00 |
|
|
877f2c34bd
|
libboard_zynq: use log logging
|
2020-05-01 01:46:42 +02:00 |
|
|
619ebf147c
|
libsupport_zynq: move mod logger to libboard_zynq
|
2020-05-01 01:33:40 +02:00 |
|
|
0d4d021b1b
|
clean up
|
2020-05-01 01:17:53 +02:00 |
|
|
d9e8a667bd
|
some macro changes and more registers
|
2020-04-29 21:19:24 +08:00 |
|
|
b22cc4e2b6
|
various control registers
|
2020-04-29 09:34:17 +08:00 |
|
|
3238dae99f
|
started writing register definitions
|
2020-04-28 23:00:47 +08:00 |
|
|
aa93794632
|
libboard_zynq: add GlobalTimer::get_us(), use in libsupport_zynq::logger
|
2020-04-25 03:01:19 +02:00 |
|
|
fe6a058a6b
|
libboard_zynq: find prescaler for GlobalTimer, rename new() to start()
|
2020-04-25 02:59:48 +02:00 |
|
|
88a2a2bc71
|
libasync, libboard_zynq: add block_async glue, make GlobalTimer sharable
|
2020-04-25 01:18:49 +02:00 |
|
|
8012573a8f
|
libboard_zynq: impl embedded_hal CountDown for GlobalTimer
|
2020-04-25 00:44:32 +02:00 |
|
|
4ab6fb6271
|
libboard_zynq: use Void in uart embedded_hal impl
|
2020-04-25 00:28:17 +02:00 |
|
|
f835192c0a
|
libboard_zynq: add GlobalTimer implementation
|
2020-04-25 00:18:45 +02:00 |
|
|
04c47b9bdb
|
libboard_zynq: impl embedded_hal serial write traits for Uart
|
2020-04-24 21:31:37 +02:00 |
|
|
f8782f3f69
|
libboard_zynq: let println!() write no '\r'
|
2020-04-20 23:44:16 +02:00 |
|
|
4b346f5c55
|
libboard_zynq: fix flash manual_mode chip_index
|
2020-04-10 20:41:16 +02:00 |
|
|
2dda3ca4e6
|
libboard_zynq: delint
|
2020-04-10 20:41:16 +02:00 |
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