11 Commits (a73df780d0d0e757738f27feac162904f5bf93f9)

Author	SHA1	Message	Date
pca006132	a73df780d0	libboard_zynq/slcr: fixed boot mode pins value ... Notice that the bits in the table in UG585 are out of order.	2020-08-31 12:35:11 +08:00
Harry Ho	1a96a7550a	libboard_zynq: make RegisterBlock constructors more consistent	2020-08-13 14:49:26 +08:00
Harry Ho	16b2df91ca	i2c: fix GPIO register mapping, I2C control & EEPROM write operations	2020-08-07 11:10:18 +08:00
Sebastien Bourdeauducq	371e59cef5	libboard_zynq: add fpgax_clk_ctrl registers	2020-07-07 19:37:51 +08:00
Sebastien Bourdeauducq	0c60d684e4	slcr: remove soft reset ... Does not work and probably difficult to get to work.	2020-07-06 13:06:10 +08:00
pca006132	236592ae66	SDIO module completed	2020-06-05 12:27:12 +08:00
Astro	0c48dd934e	libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en	2020-05-10 22:14:55 +02:00
Astro	8a98cef3fc	libboard_zynq: fix some hw setup	2020-04-03 00:17:25 +02:00
Astro	29bf29a037	add some fpga regs	2020-03-25 13:02:01 +01:00
Astro	99a2e5d621	libboard_zynq::slcr: fix arm_clk_ctrl srcsel, doc	2020-01-23 23:14:50 +01:00
Astro	cf1983e543	split into lib{register, cortex_a9, board_zynq, board_zc706} crates	2019-12-17 23:35:58 +01:00