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zynq-rs
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7 Commits

Author SHA1 Message Date
pca006132 02c67051e8 CPU options for better performance 
L2 cache options and prefetch options
 2020-09-04 16:38:48 +08:00
Astro 191abf6b8f mpidr: wrap with proper bitfield getters 
Prevents callers from dealing with CORE_MASK.
 2020-07-08 00:04:54 +02:00
Astro 2c756ba32e libcortex_a9: migrate from asm! to llvm_asm! to avoid future breakage 2020-05-01 01:11:35 +02:00
Sebastien Bourdeauducq 614b1ef350 regs: add MVBAR and HVBAR 2020-04-27 12:49:18 +08:00
Sebastien Bourdeauducq fefd2a4ceb regs: add VBAR 2020-04-27 12:34:15 +08:00
Astro 1e5fe1b836 regs: add more #[inline] annotations 
reduces .text size by 740 bytes
 2020-02-03 00:50:13 +01:00
Astro cf1983e543 split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00