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e248d3d3b1
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zynq::ddr: optimize memtest
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2019-10-31 01:32:45 +01:00 |
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91bab76ab6
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zynq::ddr: fix usable ram size
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2019-10-31 01:27:49 +01:00 |
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ceeaa6427e
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zynq::ddr: fix typo
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2019-10-28 23:58:25 +01:00 |
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fc39885d3b
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zynq::ddr: fix clock setup
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2019-10-28 00:43:09 +01:00 |
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f199ac68b4
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zynq::ddr: don't overwrite slcr.ddr_pll_ctrl
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2019-10-27 22:54:34 +01:00 |
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637bb35f43
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zynq::ddr: fix memtest progress calculation
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2019-10-27 20:38:35 +01:00 |
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85bd506132
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zynq::ddr: parameters
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2019-10-27 20:38:06 +01:00 |
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27114aec62
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zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
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2019-10-27 20:30:56 +01:00 |
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9b4f07f37c
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zynq::ddr, main: parameters, memtest
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2019-10-25 23:19:34 +02:00 |
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e61d1268ac
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zynq::slcr: doc, fix
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2019-10-25 23:18:18 +02:00 |
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a4d3360a70
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zynq::slcr: implement Display for PllStatus
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2019-10-25 20:38:10 +02:00 |
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838434cdec
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zynq::ddr: wait for init
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2019-10-25 19:15:22 +02:00 |
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4cf5283ba8
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zynq::ddr: implement reset_ddrc(), add to main
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2019-10-24 01:39:14 +02:00 |
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a8886de067
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zynq::ddr: implement configure_iob()
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2019-10-24 01:24:12 +02:00 |
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afda48e3fe
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zynq::ddr: add clock_setup(), calibrate_iob_impedance()
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2019-10-22 01:25:35 +02:00 |
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c046bbf8a2
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move slcr, clocks, uart, eth into src/zynq/
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2019-10-21 22:19:03 +02:00 |
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9d725bcf0f
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zynq::ddr: init with clock setup
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2019-10-21 22:12:10 +02:00 |
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83b8bb096a
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add zynq::axi_gp
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2019-10-19 01:46:43 +02:00 |
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b541160f38
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add zynq::axi_hp
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2019-10-18 23:46:00 +02:00 |
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