forked from M-Labs/zynq-rs
delint
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b1472096ba
commit
3eb7fce572
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@ -14,11 +14,11 @@ use alloc::{vec, vec::Vec, alloc::Layout};
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use core::alloc::GlobalAlloc;
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use core::ptr::NonNull;
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use core::cell::RefCell;
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use core::mem::{uninitialized, transmute};
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use core::mem::transmute;
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use r0::zero_bss;
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use compiler_builtins as _;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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use linked_list_allocator::Heap;
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@ -146,7 +146,7 @@ fn main() {
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let mut time = 0u32;
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loop {
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time += 1;
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let timestamp = Instant::from_millis(time.into());
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let timestamp = Instant::from_millis(time);
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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@ -0,0 +1,185 @@
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#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
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#![feature(compiler_builtins_lib)]
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#![feature(never_type)]
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// TODO: disallow unused/dead_code when code moves into a lib crate
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#![allow(dead_code)]
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use core::mem::{uninitialized, transmute};
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use r0::zero_bss;
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use compiler_builtins as _;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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mod regs;
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mod cortex_a9;
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mod clocks;
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mod slcr;
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mod uart;
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mod stdio;
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mod eth;
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use crate::regs::{RegisterR, RegisterW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __stack_start: u32;
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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match MPIDR.read() & CORE_MASK {
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0 => {
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SP.write(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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#[naked]
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#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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main();
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panic!("return from main");
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});
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}
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fn l1_cache_init() {
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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dccisw();
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}
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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fn main() {
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println!("Main.");
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let clocks = clocks::CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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println!("CPU speeds: {}/{}/{}/{} MHz",
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clocks.cpu_6x4x() / 1_000_000,
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let eth = eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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const RX_LEN: usize = 2;
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let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
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let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN];
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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const TX_LEN: usize = 2;
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let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
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let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN];
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
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let mut eth = eth.start_tx(
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// HACK
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unsafe { transmute(tx_descs.as_mut()) },
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unsafe { transmute(tx_buffers.as_mut()) },
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);
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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let local_addr = IpAddress::v4(10, 0, 0, 1);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let mut neighbor_storage = [None; 16];
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.neighbor_cache(neighbor_cache)
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.finalize();
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let mut sockets_storage = [
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None, None, None, None,
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None, None, None, None
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];
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let mut sockets = SocketSet::new(&mut sockets_storage[..]);
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let mut time = 0u32;
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loop {
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time += 1;
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let timestamp = Instant::from_millis(time.into());
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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Err(e) => {
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println!("poll error: {}", e);
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}
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}
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// match eth.recv_next() {
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// Ok(Some(pkt)) => {
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// print!("eth: rx {} bytes", pkt.len());
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// for b in pkt.iter() {
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// print!(" {:02X}", b);
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// }
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// println!("");
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// }
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// Ok(None) => {}
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// Err(e) => {
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// println!("eth rx error: {:?}", e);
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// }
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// }
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// match eth.send(512) {
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// Some(mut pkt) => {
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// let mut x = 0;
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// for b in pkt.iter_mut() {
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// *b = x;
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// x += 1;
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// }
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// println!("eth tx {} bytes", pkt.len());
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// }
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// None => println!("eth tx shortage"),
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// }
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}
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}
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#[panic_handler]
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fn panic(info: &core::panic::PanicInfo) -> ! {
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println!("\nPanic: {}", info);
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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}
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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println!("PrefetchAbort");
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loop {}
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}
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#[no_mangle]
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pub unsafe extern "C" fn DataAbort() {
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println!("DataAbort");
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loop {}
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}
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@ -2,7 +2,7 @@
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use volatile_register::RW;
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use crate::{register, register_bit, register_bits, register_bits_typed};
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use crate::{register, register_bit, register_bits};
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pub unsafe fn axi_hp0() -> &'static RegisterBlock {
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&*(0xF8008000 as *const _)
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use volatile_register::{RO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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use crate::{register, register_bit, register_bits_typed};
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#[repr(u8)]
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pub enum DataBusWidth {
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@ -170,7 +170,8 @@ register_bit!(ddrc_ctrl, powerdown_en, 1);
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register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
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// (ddrc_ctrl) ...
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/// Controller operation mode status
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register!(mode_sts_reg, ModeStsReg, RO, u32);
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// Controller operation mode status
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register!(mode_sts_reg,
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ModeStsReg, RO, u32);
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register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
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// (mode_sts_reg) ...
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