forked from M-Labs/zynq-rs
add register_bits_typed! macro
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785e726661
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179c617904
28
src/regs.rs
28
src/regs.rs
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@ -164,6 +164,34 @@ macro_rules! register_bits {
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);
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}
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/// Define a multi-bit field of a register, coerced to a certain type
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///
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/// Because read bits are just transmuted to the `$type`, its
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/// definition must be annotated with `#[repr($bit_type)]`!
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#[macro_export]
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macro_rules! register_bits_typed {
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($mod_name: ident, $name: ident, $bit_type: ty, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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impl $mod_name::Read {
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pub fn $name(&self) -> $type {
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use bit_field::BitField;
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let bits = self.inner.get_bits($bit_begin..=$bit_end) as $bit_type;
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unsafe { core::mem::transmute(bits) }
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}
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}
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impl $mod_name::Write {
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pub fn $name(mut self, value: $type) -> Self {
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use bit_field::BitField;
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let bits = (value as $bit_type).into();
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self.inner.set_bits($bit_begin..=$bit_end, bits);
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self
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}
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}
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);
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}
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#[macro_export]
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macro_rules! register_at {
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($name: ident, $addr: expr, $ctor: ident) => (
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11
src/slcr.rs
11
src/slcr.rs
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@ -1,8 +1,11 @@
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///! Register definitions for System Level Control
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_at, regs::RegisterW, regs::RegisterRW};
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use crate::{register, register_at,
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register_bit, register_bits, register_bits_typed,
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regs::RegisterW, regs::RegisterRW};
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#[repr(u8)]
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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@ -246,7 +249,7 @@ register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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register_bits_typed!(uart_clk_ctrl, srcsel, u8, PllSource, 4, 5);
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register_at!(UartClkCtrl, 0xF8000154, new);
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impl UartClkCtrl {
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pub fn enable_uart0(&mut self) {
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@ -255,7 +258,7 @@ impl UartClkCtrl {
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.srcsel(PllSource::IoPll)
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.clkact0(true)
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})
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}
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@ -266,7 +269,7 @@ impl UartClkCtrl {
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.srcsel(PllSource::IoPll)
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.clkact1(true)
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})
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}
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@ -65,11 +65,10 @@ impl Uart {
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// * 1 stop bit
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// * Normal channel mode
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// * No parity
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let parity_mode = regs::ParityMode::None;
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self.regs.mode.write(
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regs::Mode::zeroed()
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.par(parity_mode as u8)
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.chmode(regs::ChannelMode::Normal as u8)
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.par(regs::ParityMode::None)
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.chmode(regs::ChannelMode::Normal)
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);
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// Configure the Baud Rate
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@ -1,7 +1,8 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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use crate::{register, register_bit, register_bits, register_bits_typed, register_at, regs::*};
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#[repr(u8)]
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pub enum ChannelMode {
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Normal = 0b00,
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AutomaticEcho = 0b01,
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@ -9,6 +10,7 @@ pub enum ChannelMode {
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RemoteLoopback = 0b11,
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}
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#[repr(u8)]
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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@ -17,6 +19,7 @@ pub enum ParityMode {
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None = 0b100,
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}
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#[repr(u8)]
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pub enum StopBits {
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One = 0b00,
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OneAndHalf = 0b01,
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@ -60,11 +63,11 @@ register_bit!(control, stpbrk, 8);
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register!(mode, Mode, RW, u32);
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/// Channel mode: Defines the mode of operation of the UART.
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register_bits!(mode, chmode, u8, 8, 9);
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register_bits_typed!(mode, chmode, u8, ChannelMode, 8, 9);
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/// Number of stop bits
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register_bits!(mode, nbstop, u8, 6, 7);
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register_bits_typed!(mode, nbstop, u8, StopBits, 6, 7);
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/// Parity type select
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register_bits!(mode, par, u8, 3, 5);
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register_bits_typed!(mode, par, u8, ParityMode, 3, 5);
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/// Character length select
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register_bits!(mode, chrl, u8, 1, 2);
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/// Clock source select
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