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0b0ca8de49
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analyzer: drive wid and wstrb
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2020-07-15 23:11:19 +08:00 |
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8e758ecc17
|
add RTIO analyzer core (untested)
|
2020-07-15 23:06:34 +08:00 |
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b68cb137e5
|
dma: style
|
2020-07-15 23:06:14 +08:00 |
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92405ffe91
|
logger: changed from RefCell to Mutex.
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2020-07-15 17:04:16 +08:00 |
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2568d62865
|
mgmt: fixed pull log
|
2020-07-15 16:05:00 +08:00 |
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5149d37be9
|
szl: added cache flush and memory barriers.
Resolves #50.
|
2020-07-14 17:02:42 +08:00 |
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8e3574080c
|
core1: added cache flush and barriers.
|
2020-07-14 10:53:35 +08:00 |
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49d93e20dd
|
dyld: add Image.rebind()
|
2020-07-14 01:31:54 +02:00 |
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12ba867268
|
dma: fix and cleanup test
|
2020-07-13 18:58:08 +08:00 |
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5c3c3c26b5
|
dma: fix inflight_cnt and eop generation
|
2020-07-13 18:51:55 +08:00 |
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fa2d71615a
|
report async RTIO errors
|
2020-07-13 16:06:05 +08:00 |
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b42ab0634b
|
complete RTIO exceptions
|
2020-07-13 15:47:34 +08:00 |
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62f39e2c08
|
mgmt: Implemented network log access.
|
2020-07-13 15:15:06 +08:00 |
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855b26aa19
|
Logger: ported log_buffer.
|
2020-07-13 14:59:56 +08:00 |
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ea96cf96d3
|
dma: add simulation test (WIP)
|
2020-07-13 12:04:10 +08:00 |
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|
|
f1f7fe8da6
|
fix gateware pure build
|
2020-07-13 10:44:25 +08:00 |
|
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|
10888cc6c6
|
dma: remove unneeded import
|
2020-07-13 10:42:02 +08:00 |
|
|
|
a7073edf79
|
add DMA core (untested)
|
2020-07-13 10:37:17 +08:00 |
|
|
|
d79da19956
|
README: style
|
2020-07-11 19:02:37 +08:00 |
|
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|
44e84cf7d4
|
README: typo/style
|
2020-07-11 19:01:45 +08:00 |
|
|
|
8085e7d646
|
README: document config
|
2020-07-11 19:00:19 +08:00 |
|
|
|
10643d878c
|
README: fix md syntax
|
2020-07-11 18:10:25 +08:00 |
|
|
|
76dd84e237
|
README: update
|
2020-07-11 18:08:49 +08:00 |
|
|
|
e3ff21b1b5
|
create gateware folder
|
2020-07-11 17:49:54 +08:00 |
|
|
|
7aec419ed6
|
kernel: added core1 instruction cache flush
|
2020-07-10 17:21:55 +08:00 |
|
|
|
68d27ca2ee
|
comms: removed core1 restart
|
2020-07-10 17:21:55 +08:00 |
|
|
|
407e18a6a0
|
fix typos
|
2020-07-10 16:36:45 +08:00 |
|
|
|
2d58193930
|
Panic: single line backtrace for addr2line.
|
2020-07-10 12:26:28 +08:00 |
|
|
|
c935e450df
|
makefile: automate runtime dependencies
|
2020-07-09 09:41:45 +08:00 |
|
|
|
656e768f06
|
makefile: update dependencies
|
2020-07-09 09:31:36 +08:00 |
|
|
|
2c1773b91b
|
kernel: refactor main_core1 into KernelImage
|
2020-07-08 23:49:43 +02:00 |
|
|
|
b3d4590eec
|
kernel: split into {api,control,core1,rpc}
|
2020-07-08 23:49:32 +02:00 |
|
|
|
68045ce0c5
|
mark RTIO clock as asychronous to system clock
|
2020-07-08 20:37:53 +08:00 |
|
|
|
7ee67db8e3
|
use IOSERDES TTL
|
2020-07-08 20:02:46 +08:00 |
|
|
|
bd7d58e239
|
add RTIO PLL and clock source selection
|
2020-07-08 19:58:13 +08:00 |
|
|
|
6454315cd2
|
config: refactor and share
|
2020-07-08 19:24:26 +08:00 |
|
|
|
e263814546
|
Kernel: Added startup kernel
|
2020-07-08 15:54:50 +08:00 |
|
|
|
67ff3c36e2
|
drop FSBL
All SZL and Zynq startup issues seem resolved.
|
2020-07-07 19:44:14 +08:00 |
|
|
|
a8de572014
|
set up PL clocks
|
2020-07-07 19:40:32 +08:00 |
|
|
|
e750b61973
|
shell.nix: add binutils
|
2020-07-07 19:39:30 +08:00 |
|
|
|
b13da96835
|
increase CSR bus width to 32 bits
Before:
Minimum interval for sustained TTL output switching ... 1.554e-06
After:
Minimum interval for sustained TTL output switching ... 5.17e-07
|
2020-07-07 17:22:07 +08:00 |
|
|
|
7bfe882710
|
eh_artiq: reduce verbosity
|
2020-07-07 17:21:28 +08:00 |
|
|
|
c071507ff8
|
RTIO: implemented exceptions
|
2020-07-07 16:26:33 +08:00 |
|
|
|
f1750cf8cd
|
Kernel: Fixed use-after-free
|
2020-07-07 15:51:12 +08:00 |
|
|
|
0f797284e2
|
SdReader: fixed write cache bug.
|
2020-07-07 14:02:13 +08:00 |
|
|
|
e6cf3e90d3
|
update zc706
|
2020-07-07 12:50:05 +08:00 |
|
|
|
0119022b2c
|
remove compiler warning
|
2020-07-06 21:55:30 +08:00 |
|
|
|
de2c2af523
|
use new exception vectors
|
2020-07-06 21:16:32 +08:00 |
|
|
|
8c0b7cdcf2
|
runtime: adjust stack and heap sizes
|
2020-07-06 20:48:22 +08:00 |
|
|
|
7661b2a288
|
remove unused import
|
2020-07-06 20:41:24 +08:00 |
|
