forked from M-Labs/artiq-zynq
dma: fix and cleanup test
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5c3c3c26b5
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@ -26,7 +26,6 @@ class AXIMemorySim:
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while True:
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if len(self.queue) < self.max_queue:
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request = yield from self.bus.read_ar()
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print(request.addr)
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self.queue.append(request)
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else:
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yield
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@ -44,7 +43,7 @@ class AXIMemorySim:
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if request.addr % self.align:
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raise ValueError
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addr = request.addr//self.align + i
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if addr < len(self.queue):
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if addr < len(self.data):
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data = self.data[addr]
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else:
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data = 0
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