forked from M-Labs/zynq-rs
103 lines
3.2 KiB
Rust
103 lines
3.2 KiB
Rust
///! FPD clock and reset control
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use volatile_register::{RO, RW, WO};
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use libregister::{
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register, register_at,
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register_bit, register_bits,
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};
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#[repr(C)]
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pub struct RegisterBlock {
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// CRF_APB
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pub err_ctrl: RW<u32>,
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pub ir_status: RW<u32>, // todo: WTC LSB
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pub ir_mask: RO<u32>,
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pub ir_enable: WO<u32>,
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pub ir_disable: WO<u32>,
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pub crf_wprot: RW<u32>,
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pub apu_pll_ctrl: PllCtrl,
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pub apu_pll_cfg: PllCfg,
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pub apu_pll_frac_cfg: PllFracCfg,
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pub ddr_pll_ctrl: PllCtrl,
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pub ddr_pll_cfg: PllCfg,
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pub ddr_pll_frac_cfg: PllFracCfg,
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pub video_pll_ctr: PllCtrl,
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pub video_pll_cfg: PllCfg,
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pub video_pll_frac_cfg: PllFracCfg,
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pub pll_status: PllStatus,
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pub apu_pll_to_lpd_ctrl: PllToLpdCtrl,
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pub ddr_pll_to_lpd_ctrl: PllToLpdCtrl,
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pub video_pll_to_lpd_ctrl: PllToLpdCtrl,
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reserved1: [u32; 3],
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pub apu_clk_ctrl: ApuClkCtrl,
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pub dbg_trace_clk_ctrl: RW<u32>,
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pub dbg_fpd_clk_ctrl: RW<u32>,
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reserved2: [u32; 1],
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pub dp_video_clk_ctrl: RW<u32>,
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pub dp_audio_clk_ctrl: RW<u32>,
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reserved3: [u32; 1],
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pub dp_sys_clk_ctrl: RW<u32>,
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pub ddr_clk_ctrl: DdrClkCtrl,
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pub gpu_clk_ctrl: RW<u32>,
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reserved4: [u32; 6],
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pub sata_clk_ctrl: RW<u32>,
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reserved5: [u32; 4],
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pub pcie_clk_ctrl: RW<u32>,
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pub fpd_dma_clk_ctrl: RW<u32>,
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pub dp_dma_clk_ctrl: RW<u32>,
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pub topsw_main_clk_ctrl: RW<u32>,
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pub topsw_lsbus_clk_ctrl: RW<u32>,
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reserved6: [u32; 8],
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pub dbg_tstmp_clk_ctrl: RW<u32>,
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reserved7: [u32; 1],
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pub rst_fpd_top: RW<u32>,
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pub rst_fpd_apu: RW<u32>,
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pub rst_ddr_ss: RW<u32>,
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}
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register_at!(RegisterBlock, 0xFD1A_0000, crf_apb);
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register!(pll_ctrl, PllCtrl, RW, u32);
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register_bits!(pll_ctrl, post_src, u8, 24, 26);
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register_bits!(pll_ctrl, pre_src, u8, 20, 22);
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register_bit!(pll_ctrl, div2, 16);
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register_bits!(pll_ctrl, fbdiv, u8, 8, 14);
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register_bit!(pll_ctrl, bypass, 3);
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register_bit!(pll_ctrl, reset, 0);
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register!(pll_cfg, PllCfg, RW, u32);
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register_bits!(pll_cfg, lock_dly, u8, 25, 31);
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register_bits!(pll_cfg, lock_cnt, u16, 13, 22);
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register_bits!(pll_cfg, lfhf, u8, 10, 11);
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register_bits!(pll_cfg, cp, u8, 5, 8);
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register_bits!(pll_cfg, res, u8, 0, 3);
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register!(pll_frac_cfg, PllFracCfg, RW, u32);
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register_bit!(pll_frac_cfg, enabled, 31);
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register_bits!(pll_frac_cfg, data, u16, 0, 15);
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register!(pll_status, PllStatus, RO, u32);
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register_bit!(pll_status, video_pll_stable, 5);
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register_bit!(pll_status, ddr_pll_stable, 4);
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register_bit!(pll_status, apu_pll_stable, 3);
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register_bit!(pll_status, video_pll_lock, 2);
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register_bit!(pll_status, ddr_pll_lock, 1);
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register_bit!(pll_status, apu_pll_lock, 0);
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register!(pll_to_lpd_ctrl, PllToLpdCtrl, RW, u32);
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register_bits!(pll_to_lpd_ctrl, divisor0, u8, 8, 13);
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register!(apu_clk_ctrl, ApuClkCtrl, RW, u32);
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register_bit!(apu_clk_ctrl, clkact_half, 25);
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register_bit!(apu_clk_ctrl, clkact_full, 24);
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register_bits!(apu_clk_ctrl, divisor0, u8, 8, 13);
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// 000: APU PLL
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// 010: DDR PLL
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// 011: Video PLL
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register_bits!(apu_clk_ctrl, srcsel, u8, 0, 2);
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register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
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register_bits!(ddr_clk_ctrl, divisor0, u8, 8, 13);
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// 000: DDR PLL
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// 001: Video PLL
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register_bits!(ddr_clk_ctrl, srcsel, u8, 0, 2);
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