forked from M-Labs/zynq-rs
77 lines
2.3 KiB
Rust
77 lines
2.3 KiB
Rust
/// ADMA library
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use core::mem::MaybeUninit;
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use super::SDIO;
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use libcortex_a9::cache;
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use libregister::{
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register, register_bit,
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RegisterR, RegisterW, RegisterRW, VolatileCell,
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};
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#[repr(C, align(4))]
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pub struct Adma2Desc32 {
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attribute: Desc32Attribute,
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length: VolatileCell<u16>,
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address: VolatileCell<u32>,
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}
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const DESC_MAX_LENGTH: u32 = 65536;
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register!(desc32_attribute, Desc32Attribute, VolatileCell, u16);
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register_bit!(desc32_attribute, trans, 5);
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register_bit!(desc32_attribute, int, 2);
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register_bit!(desc32_attribute, end, 1);
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register_bit!(desc32_attribute, valid, 0);
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pub struct Adma2DescTable([Adma2Desc32; 32]);
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impl Adma2DescTable {
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pub fn new() -> Self {
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let table = MaybeUninit::zeroed();
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let table = unsafe { table.assume_init() };
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Adma2DescTable(table)
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}
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/// Initialize the table and setup `adma_system_address`
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pub fn setup(&mut self, sdio: &mut SDIO, blk_cnt: u32, buffer: &[u8]) {
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let descr_table = &mut self.0;
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let blk_size = sdio
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.regs
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.block_size_block_count
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.read()
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.transfer_block_size() as u32;
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let total_desc_lines = if blk_size * blk_cnt < DESC_MAX_LENGTH {
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1
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} else {
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blk_size * blk_cnt / DESC_MAX_LENGTH
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+ if (blk_size * blk_cnt) % DESC_MAX_LENGTH == 0 {
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0
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} else {
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1
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}
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} as usize;
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let ptr = buffer.as_ptr() as u32;
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for desc_num in 0..total_desc_lines {
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descr_table[desc_num].address.set(ptr + (desc_num as u32) * DESC_MAX_LENGTH);
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descr_table[desc_num].attribute.write(
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Desc32Attribute::zeroed()
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.trans(true)
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.valid(true)
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);
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// 0 is the max length (65536)
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descr_table[desc_num].length.set(0);
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}
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descr_table[total_desc_lines - 1].attribute.modify(|_, w| w.end(true));
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descr_table[total_desc_lines - 1].length.set(
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(blk_cnt * blk_size - ((total_desc_lines as u32) - 1) * DESC_MAX_LENGTH) as u16,
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);
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unsafe {
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sdio.regs
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.adma_system_address
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.write(descr_table.as_ptr() as u32);
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}
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cache::dcci_slice(descr_table);
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}
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}
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