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zynq-rs
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145 Commits 4 Branches 0 Tags 1.2 MiB
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25 Commits

Author SHA1 Message Date
Astro 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 2019-11-04 02:31:40 +01:00
Astro 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 2019-11-04 02:30:00 +01:00
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation 
off-by-one, didn't change behavior.
 2019-11-03 02:23:16 +01:00
Astro 04e816d99e zynq::slcr: fix a bitfield index 
that didn't solve our problems.
 2019-11-03 02:01:42 +01:00
Astro 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 2019-10-31 20:48:07 +01:00
Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell 
vcell can be initialized cleanly.
 2019-10-31 03:15:13 +01:00
Astro e248d3d3b1 zynq::ddr: optimize memtest 2019-10-31 01:32:45 +01:00
Astro 91bab76ab6 zynq::ddr: fix usable ram size 2019-10-31 01:27:49 +01:00
Astro ceeaa6427e zynq::ddr: fix typo 2019-10-28 23:58:25 +01:00
Astro fc39885d3b zynq::ddr: fix clock setup 2019-10-28 00:43:09 +01:00
Astro f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl 2019-10-27 22:54:34 +01:00
Astro 637bb35f43 zynq::ddr: fix memtest progress calculation 2019-10-27 20:38:35 +01:00
Astro 85bd506132 zynq::ddr: parameters 2019-10-27 20:38:06 +01:00
Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage 
this seems to make DDR RAM work.
 2019-10-27 20:30:56 +01:00
Astro 9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
Astro e61d1268ac zynq::slcr: doc, fix 2019-10-25 23:18:18 +02:00
Astro a4d3360a70 zynq::slcr: implement Display for PllStatus 2019-10-25 20:38:10 +02:00
Astro 838434cdec zynq::ddr: wait for init 2019-10-25 19:15:22 +02:00
Astro 4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 2019-10-24 01:39:14 +02:00
Astro a8886de067 zynq::ddr: implement configure_iob() 2019-10-24 01:24:12 +02:00
Astro afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() 2019-10-22 01:25:35 +02:00
Astro c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
Astro 9d725bcf0f zynq::ddr: init with clock setup 2019-10-21 22:12:10 +02:00
Astro 83b8bb096a add zynq::axi_gp 2019-10-19 01:46:43 +02:00
Astro b541160f38 add zynq::axi_hp 2019-10-18 23:46:00 +02:00