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libboard_zynq/slcr: fixed boot mode pins value 

Notice that the bits in the table in UG585 are out of order.
This commit is contained in:
pca006132 2020-08-31 12:35:11 +08:00
parent e73ec731aa
commit a73df780d0
1 changed files with 8 additions and 5 deletions
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13
libboard_zynq/src/slcr.rs
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@ -590,16 +590,19 @@ register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
#[derive(Clone, Copy, Debug, PartialEq)] #[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)] #[repr(u8)]
pub enum BootModePins { pub enum BootModePins {
// CAUTION!
// The BOOT_MODE bits table 6-4 in UG585 are *out of order*.
Jtag = 0b000, Jtag = 0b000,
Nor = 0b001, Nor = 0b010,
Nand = 0b010, Nand = 0b100,
QuadSpi = 0b100, QuadSpi = 0b001,
SdCard = 0b110, SdCard = 0b101,
} }
register!(boot_mode, BootMode, RO, u32); register!(boot_mode, BootMode, RO, u32);
register_bit!(boot_mode, pll_bypass, 4); register_bit!(boot_mode, pll_bypass, 4);
register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 3); register_bit!(boot_mode, jtag_routing, 3);
register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 2);
register!(pss_rst_ctrl, PssRstCtrl, RW, u32); register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
register_bit!(pss_rst_ctrl, soft_rst, 1); register_bit!(pss_rst_ctrl, soft_rst, 1);