zync_us/slcr: add MIO SLCRs

libboard_zynq_us/src/slcr/iou_slcr.rs

@@ -0,0 +1,115 @@
+///! IOU SLCR for MIO pin configuration
+
+use volatile_register::{RO, RW, WO};
+use libregister::{
+    register, register_at,
+    register_bit, register_bits, register_bits_typed,
+    RegisterW, RegisterRW,
+};
+
+
+#[repr(C)]
+pub struct RegisterBlock {
+    pub mio_pin: [MioPin; 78],
+    pub bank0_drive0: BankDriveCtrl,
+    pub bank0_drive1: BankDriveCtrl,
+    pub bank0_input_ctrl: BankInputCtrl,
+    pub bank0_pull_ctrl: BankPullCtrl,
+    pub bank0_pull_enable: BankPullEnable,
+    pub bank0_slew_ctrl: BankSlewCtrl,
+    pub bank0_status: BankStatus,
+    pub bank1_drive0: BankDriveCtrl,
+    pub bank1_drive1: BankDriveCtrl,
+    pub bank1_input_ctrl: BankInputCtrl,
+    pub bank1_pull_ctrl: BankPullCtrl,
+    pub bank1_pull_enable: BankPullEnable,
+    pub bank1_slew_ctrl: BankSlewCtrl,
+    pub bank1_status: BankStatus,
+    pub bank2_drive0: BankDriveCtrl,
+    pub bank2_drive1: BankDriveCtrl,
+    pub bank2_input_ctrl: BankInputCtrl,
+    pub bank2_pull_ctrl: BankPullCtrl,
+    pub bank2_pull_enable: BankPullEnable,
+    pub bank2_slew_ctrl: BankSlewCtrl,
+    pub bank2_status: BankStatus,
+    reserved1: [u32; 5],
+    pub mio_loopback: RW<u32>,
+    pub mio_mst_tri0: RW<u32>,
+    pub mio_mst_tri1: RW<u32>,
+    pub mio_mst_tri2: RW<u32>,
+    pub wdt_clk_sel: RW<u32>, // 0 = internal APB clock, 1 = external
+    pub can_mio_ctrl: RW<u32>,
+    pub gem_clk_ctrl: RW<u32>,
+    pub sdio_clk_ctrl: RW<u32>,
+    pub ctrl_reg_sd: RW<u32>,
+    pub sd_itap_dly: RW<u32>,
+    pub sd_otap_dly_sel: RW<u32>,
+    pub sd_cfg1: RW<u32>,
+    pub sd_cfg2: RW<u32>,
+    pub sd_cfg3: RW<u32>,
+    pub sd_init_preset: RW<u32>,
+    pub sd_speed_preset: RW<u32>,
+    pub sd_hspeed_preset: RW<u32>,
+    pub sd_sdr12_preset: RW<u32>,
+    pub sd_sdr25_preset: RW<u32>,
+    pub sd_sdr50_preset: RW<u32>,
+    reserved2: [u32; 1],
+    pub sd_sdr104_preset: RW<u32>,
+    pub sd_ddr50_preset: RW<u32>,
+    pub sd_max_cur_18: RW<u32>,
+    pub sd_max_cur_30: RW<u32>,
+    pub sd_max_cur_33: RW<u32>,
+    pub sd_dll_ctrl: RW<u32>,
+    pub sd_cdn_ctrl: RW<u32>,
+    pub gem_ctrl: RW<u32>,
+    reserved3: [u32; 7],
+    pub iou_ttc_apb_clk: RW<u32>,
+    reserved4: [u32; 3],
+    pub iou_tapdly_bypass: RW<u32>,
+    reserved5: [u32; 3],
+    pub iou_coherent_ctrl: RW<u32>,
+    pub video_pss_clk_sel: RW<u32>,
+    pub iou_interconnect_route: RW<u32>,
+    reserved6: [u32; 125],
+    pub ctrl: RW<u32>,
+    reserved7: [u32; 63],
+    pub isr: RW<u32>, // todo: WTC LSB
+    pub imr: RO<u32>,
+    pub ier: WO<u32>,
+    pub idr: WO<u32>,
+    pub itr: WO<u32>,
+}
+register_at!(RegisterBlock, 0xFF18_0000, iou_slcr);
+
+
+register!(mio_pin, MioPin, RW, u32);
+register_bits!(mio_pin, l3_sel, u8, 5, 7);
+register_bits!(mio_pin, l2_sel, u8, 3, 4);
+register_bit!(mio_pin, l1_sel, 2);
+register_bit!(mio_pin, l0_sel, 1);
+
+register!(bank_drive_ctrl, BankDriveCtrl, RW, u32);
+register_bits!(bank_drive_ctrl, drive, u32, 0, 25);
+
+// 0 = CMOS, 1 = Schmitt
+register!(bank_input_ctrl, BankInputCtrl, RW, u32);
+register_bits!(bank_input_ctrl, schmitt, u32, 0, 25);
+
+// 0 = down, 1 = up
+register!(bank_pull_ctrl, BankPullCtrl, RW, u32);
+register_bits!(bank_pull_ctrl, pull_up, u32, 0, 25);
+
+register!(bank_pull_enable, BankPullEnable, RW, u32);
+register_bits!(bank_pull_enable, pull_enable, u32, 0, 25);
+
+// 0 = fast, 1 = slow
+register!(bank_slew_ctrl, BankSlewCtrl, RW, u32);
+register_bits!(bank_slew_ctrl, slow_slew, u32, 0, 25);
+
+// 0 = 2.5 or 3.3V, 1 = 1.8V
+register!(bank_status, BankStatus, RO, u32);
+register_bit!(bank_status, voltage_mode, 0);
+
+
+// todo: impl for MioPin (or RegisterBlock?) to make drive ctrl less obnoxious
+// might as well toss in convenience functions for pull up/down, etc.

libboard_zynq_us/src/slcr/mod.rs

@@ -3,6 +3,7 @@ pub mod crf_apb;
 // APU
 // FPD_SLCR
 // FPD_SLCR_SECURE
+pub mod iou_slcr;
 // IOU_SLCR
 // IOU_SECURE_SLCR
 // IOU_SCNTRS