forked from M-Labs/zynq-rs
working openocd scripts for zc706 and cora-z7-10
This commit is contained in:
parent
d6b2321fee
commit
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10
README.md
10
README.md
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@ -36,14 +36,16 @@ Proceed using gdb with `load`, `c`
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## Using OpenOCD
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## Using OpenOCD
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### Resources for the ZC706
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### Running on the ZC706
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https://devel.rtems.org/wiki/Debugging/OpenOCD/Xilinx_Zynq
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```shell
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https://github.com/nathanrossi/meta-random/tree/master/openocd-zynq
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nix-shell --command "cargo build --release"
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openocd -f openocd/zc706.cfg
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```
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### Running on the Cora Z7-10
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### Running on the Cora Z7-10
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```shell
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```shell
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nix-shell --command "cargo build --release --no-default-features --features=target_cora_z7_10"
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nix-shell --command "cargo build --release --no-default-features --features=target_cora_z7_10"
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openocd -f cora-z7-10.cfg
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openocd -f openocd/cora-z7-10.cfg
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```
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```
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@ -1,49 +0,0 @@
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source [find interface/ftdi/digilent-hs1.cfg]
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source [find target/zynq_7000.cfg]
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set _TARGETNAME_0 "zynq.cpu0"
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set _TARGETNAME_1 "zynq.cpu1"
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set _SMP 1
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proc zynq_restart { wait } {
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global _SMP
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global _TARGETNAME_0
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global _TARGETNAME_1
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set target0 $_TARGETNAME_0
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set target1 $_TARGETNAME_1
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echo "Zynq reset, resetting the board ... "
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poll off
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#
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# Issue the reset via the SLCR
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#
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catch {
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mww phys 0xF8000008 0xDF0D
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mww phys 0xF8000200 1
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}
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echo "Zynq reset waiting for $wait msecs ... "
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sleep $wait
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#
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# Reconnect the DAP etc due to the reset.
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#
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$target0 cortex_a dbginit
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$target0 arm core_state arm
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if { $_SMP } {
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$target1 arm core_state arm
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$target1 cortex_a dbginit
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cortex_a smp_off
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}
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poll on
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#
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# We can now halt the core.
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#
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if { $_SMP } {
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targets $target1
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halt
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}
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targets $target0
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halt
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#zynq_rtems_setup
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}
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init
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zynq_restart 100
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@ -0,0 +1,41 @@
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source [find interface/ftdi/digilent-hs1.cfg]
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adapter_khz 10000
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set PL_TAPID 0x03727093
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set SMP 1
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source ./zynq-7000.cfg
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source ./xilinx-tcl.cfg
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source ./ps7_init.tcl
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reset_config srst_only srst_push_pull
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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xilinx_ps7_init
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# Disable MMU
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targets $_TARGETNAME_1
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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targets $_TARGETNAME_0
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arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
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@ -0,0 +1,19 @@
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#
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# Digilent JTAG-SMT2-NC
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#
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# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
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# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
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#
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# Based on reference sheet (above) and Xilinx KCU105 schematics
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# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
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#
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# Note that the digilent_jtag_smt2 layout does not work and hangs while
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# the ftdi_device_desc from digilent_hs2 is wrong.
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interface ftdi
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ftdi_device_desc "Digilent USB Device"
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ftdi_vid_pid 0x0403 0x6014
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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@ -0,0 +1,771 @@
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proc ps7_pll_init_data_3_0 {} {
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mwr -force 0XF8000008 0x0000DF0D
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mask_write 0XF8000110 0x003FFFF0 0x000FA220
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mask_write 0XF8000100 0x0007F000 0x00028000
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mask_write 0XF8000100 0x00000010 0x00000010
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mask_write 0XF8000100 0x00000001 0x00000001
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mask_write 0XF8000100 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000001
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mask_write 0XF8000100 0x00000010 0x00000000
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mask_write 0XF8000120 0x1F003F30 0x1F000200
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mask_write 0XF8000114 0x003FFFF0 0x0012C220
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mask_write 0XF8000104 0x0007F000 0x00020000
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mask_write 0XF8000104 0x00000010 0x00000010
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mask_write 0XF8000104 0x00000001 0x00000001
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mask_write 0XF8000104 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000002
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mask_write 0XF8000104 0x00000010 0x00000000
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mask_write 0XF8000124 0xFFF00003 0x0C200003
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mask_write 0XF8000118 0x003FFFF0 0x001452C0
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mask_write 0XF8000108 0x0007F000 0x0001E000
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mask_write 0XF8000108 0x00000010 0x00000010
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mask_write 0XF8000108 0x00000001 0x00000001
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mask_write 0XF8000108 0x00000001 0x00000000
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mask_poll 0XF800010C 0x00000004
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mask_write 0XF8000108 0x00000010 0x00000000
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mwr -force 0XF8000004 0x0000767B
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}
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proc ps7_clock_init_data_3_0 {} {
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mwr -force 0XF8000008 0x0000DF0D
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mask_write 0XF8000128 0x03F03F01 0x00700F01
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mask_write 0XF8000138 0x00000011 0x00000001
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mask_write 0XF8000140 0x03F03F71 0x00100801
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mask_write 0XF800014C 0x00003F31 0x00000501
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mask_write 0XF8000150 0x00003F33 0x00001401
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mask_write 0XF8000154 0x00003F33 0x00001402
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mask_write 0XF8000168 0x00003F31 0x00000501
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mask_write 0XF8000170 0x03F03F30 0x00200500
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mask_write 0XF80001C4 0x00000001 0x00000001
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mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
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mwr -force 0XF8000004 0x0000767B
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}
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proc ps7_ddr_init_data_3_0 {} {
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mask_write 0XF8006000 0x0001FFFF 0x00000080
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mask_write 0XF8006004 0x0007FFFF 0x00001081
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mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
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mask_write 0XF800600C 0x03FFFFFF 0x02001001
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mask_write 0XF8006010 0x03FFFFFF 0x00014001
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mask_write 0XF8006014 0x001FFFFF 0x0004159B
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mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
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mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
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mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
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mask_write 0XF8006024 0x0FFFFFC3 0x00000000
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mask_write 0XF8006028 0x00003FFF 0x00002007
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mask_write 0XF800602C 0xFFFFFFFF 0x00000008
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mask_write 0XF8006030 0xFFFFFFFF 0x00040930
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mask_write 0XF8006034 0x13FF3FFF 0x000116D4
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mask_write 0XF8006038 0x00000003 0x00000000
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mask_write 0XF800603C 0x000FFFFF 0x00000777
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mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
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mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
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mask_write 0XF8006048 0x0003F03F 0x0003C008
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mask_write 0XF8006050 0xFF0F8FFF 0x77010800
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mask_write 0XF8006058 0x00010000 0x00000000
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mask_write 0XF800605C 0x0000FFFF 0x00005003
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mask_write 0XF8006060 0x000017FF 0x0000003E
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mask_write 0XF8006064 0x00021FE0 0x00020000
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mask_write 0XF8006068 0x03FFFFFF 0x00284141
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mask_write 0XF800606C 0x0000FFFF 0x00001610
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mask_write 0XF8006078 0x03FFFFFF 0x00466111
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mask_write 0XF800607C 0x000FFFFF 0x00032222
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mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
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mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
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mask_write 0XF80060AC 0x000001FF 0x000001FE
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mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
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mask_write 0XF80060B4 0x00000200 0x00000200
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mask_write 0XF80060B8 0x01FFFFFF 0x00200066
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mask_write 0XF80060C4 0x00000003 0x00000000
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mask_write 0XF80060C8 0x000000FF 0x00000000
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mask_write 0XF80060DC 0x00000001 0x00000000
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mask_write 0XF80060F0 0x0000FFFF 0x00000000
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mask_write 0XF80060F4 0x0000000F 0x00000008
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mask_write 0XF8006114 0x000000FF 0x00000000
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mask_write 0XF8006118 0x7FFFFFCF 0x40000001
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mask_write 0XF800611C 0x7FFFFFCF 0x40000001
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mask_write 0XF8006120 0x7FFFFFCF 0x40000001
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mask_write 0XF8006124 0x7FFFFFCF 0x40000001
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mask_write 0XF800612C 0x000FFFFF 0x00033C03
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mask_write 0XF8006130 0x000FFFFF 0x00034003
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mask_write 0XF8006134 0x000FFFFF 0x0002F400
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mask_write 0XF8006138 0x000FFFFF 0x00030400
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mask_write 0XF8006140 0x000FFFFF 0x00000035
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mask_write 0XF8006144 0x000FFFFF 0x00000035
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mask_write 0XF8006148 0x000FFFFF 0x00000035
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mask_write 0XF800614C 0x000FFFFF 0x00000035
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mask_write 0XF8006154 0x000FFFFF 0x00000083
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mask_write 0XF8006158 0x000FFFFF 0x00000083
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mask_write 0XF800615C 0x000FFFFF 0x00000080
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mask_write 0XF8006160 0x000FFFFF 0x00000080
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mask_write 0XF8006168 0x001FFFFF 0x00000124
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mask_write 0XF800616C 0x001FFFFF 0x00000125
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mask_write 0XF8006170 0x001FFFFF 0x00000112
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mask_write 0XF8006174 0x001FFFFF 0x00000116
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mask_write 0XF800617C 0x000FFFFF 0x000000C3
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mask_write 0XF8006180 0x000FFFFF 0x000000C3
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mask_write 0XF8006184 0x000FFFFF 0x000000C0
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mask_write 0XF8006188 0x000FFFFF 0x000000C0
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mask_write 0XF8006190 0x6FFFFEFE 0x00040080
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mask_write 0XF8006194 0x000FFFFF 0x0001FC82
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mask_write 0XF8006204 0xFFFFFFFF 0x00000000
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mask_write 0XF8006208 0x000703FF 0x000003FF
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mask_write 0XF800620C 0x000703FF 0x000003FF
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mask_write 0XF8006210 0x000703FF 0x000003FF
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mask_write 0XF8006214 0x000703FF 0x000003FF
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mask_write 0XF8006218 0x000F03FF 0x000003FF
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mask_write 0XF800621C 0x000F03FF 0x000003FF
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mask_write 0XF8006220 0x000F03FF 0x000003FF
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mask_write 0XF8006224 0x000F03FF 0x000003FF
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mask_write 0XF80062A8 0x00000FF5 0x00000000
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mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
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mask_write 0XF80062B0 0x003FFFFF 0x00005125
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mask_write 0XF80062B4 0x0003FFFF 0x000012A8
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mask_poll 0XF8000B74 0x00002000
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mask_write 0XF8006000 0x0001FFFF 0x00000081
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mask_poll 0XF8006054 0x00000007
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}
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proc ps7_mio_init_data_3_0 {} {
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mwr -force 0XF8000008 0x0000DF0D
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mask_write 0XF8000B40 0x00000FFF 0x00000600
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mask_write 0XF8000B44 0x00000FFF 0x00000600
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mask_write 0XF8000B48 0x00000FFF 0x00000672
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mask_write 0XF8000B4C 0x00000FFF 0x00000672
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mask_write 0XF8000B50 0x00000FFF 0x00000674
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mask_write 0XF8000B54 0x00000FFF 0x00000674
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mask_write 0XF8000B58 0x00000FFF 0x00000600
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mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
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mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
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mask_write 0XF8000B6C 0x00007FFF 0x00000209
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mask_write 0XF8000B70 0x00000001 0x00000001
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mask_write 0XF8000B70 0x00000021 0x00000020
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mask_write 0XF8000B70 0x07FEFFFF 0x00000823
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mask_write 0XF8000700 0x00003FFF 0x00000600
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mask_write 0XF8000704 0x00003FFF 0x00000702
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mask_write 0XF8000708 0x00003FFF 0x00000702
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mask_write 0XF800070C 0x00003FFF 0x00000702
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mask_write 0XF8000710 0x00003FFF 0x00000702
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mask_write 0XF8000714 0x00003FFF 0x00000702
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mask_write 0XF8000718 0x00003FFF 0x00000702
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mask_write 0XF800071C 0x00003FFF 0x00000600
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mask_write 0XF8000720 0x00003FFF 0x00000700
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mask_write 0XF8000724 0x00003FFF 0x00000600
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mask_write 0XF8000728 0x00003FFF 0x00000600
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mask_write 0XF800072C 0x00003FFF 0x00000600
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mask_write 0XF8000730 0x00003FFF 0x00000600
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mask_write 0XF8000734 0x00003FFF 0x00000600
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mask_write 0XF8000738 0x00003FFF 0x00000600
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mask_write 0XF800073C 0x00003FFF 0x00000600
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mask_write 0XF8000740 0x00003FFF 0x00000302
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mask_write 0XF8000744 0x00003FFF 0x00000302
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mask_write 0XF8000748 0x00003FFF 0x00000302
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mask_write 0XF800074C 0x00003FFF 0x00000302
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mask_write 0XF8000750 0x00003FFF 0x00000302
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mask_write 0XF8000754 0x00003FFF 0x00000302
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mask_write 0XF8000758 0x00003FFF 0x00000303
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mask_write 0XF800075C 0x00003FFF 0x00000303
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mask_write 0XF8000760 0x00003FFF 0x00000303
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mask_write 0XF8000764 0x00003FFF 0x00000303
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mask_write 0XF8000768 0x00003FFF 0x00000303
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mask_write 0XF800076C 0x00003FFF 0x00000303
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mask_write 0XF8000770 0x00003FFF 0x00000304
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mask_write 0XF8000774 0x00003FFF 0x00000305
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||||||
|
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||||
|
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||||
|
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_peripherals_init_data_3_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||||
|
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||||
|
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||||
|
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||||
|
mask_write 0XE000D000 0x00080000 0x00080000
|
||||||
|
mask_write 0XF8007000 0x20000000 0x00000000
|
||||||
|
}
|
||||||
|
proc ps7_post_config_3_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||||
|
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_debug_3_0 {} {
|
||||||
|
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||||
|
}
|
||||||
|
proc ps7_pll_init_data_2_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||||
|
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||||
|
mask_write 0XF8000100 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000100 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000100 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000001
|
||||||
|
mask_write 0XF8000100 0x00000010 0x00000000
|
||||||
|
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||||
|
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||||
|
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||||
|
mask_write 0XF8000104 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000104 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000104 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000002
|
||||||
|
mask_write 0XF8000104 0x00000010 0x00000000
|
||||||
|
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||||
|
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||||
|
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||||
|
mask_write 0XF8000108 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000108 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000108 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000004
|
||||||
|
mask_write 0XF8000108 0x00000010 0x00000000
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_clock_init_data_2_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||||
|
mask_write 0XF8000138 0x00000011 0x00000001
|
||||||
|
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||||
|
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||||
|
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||||
|
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||||
|
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||||
|
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||||
|
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||||
|
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_ddr_init_data_2_0 {} {
|
||||||
|
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||||
|
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||||
|
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||||
|
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||||
|
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||||
|
mask_write 0XF8006014 0x001FFFFF 0x0004159B
|
||||||
|
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
|
||||||
|
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||||
|
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||||
|
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||||
|
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||||
|
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||||
|
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||||
|
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||||
|
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||||
|
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||||
|
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||||
|
mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
|
||||||
|
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||||
|
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||||
|
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||||
|
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||||
|
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||||
|
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||||
|
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||||
|
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||||
|
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||||
|
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||||
|
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||||
|
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||||
|
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||||
|
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||||
|
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||||
|
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||||
|
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||||
|
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||||
|
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||||
|
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||||
|
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||||
|
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||||
|
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||||
|
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF800612C 0x000FFFFF 0x00033C03
|
||||||
|
mask_write 0XF8006130 0x000FFFFF 0x00034003
|
||||||
|
mask_write 0XF8006134 0x000FFFFF 0x0002F400
|
||||||
|
mask_write 0XF8006138 0x000FFFFF 0x00030400
|
||||||
|
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006154 0x000FFFFF 0x00000083
|
||||||
|
mask_write 0XF8006158 0x000FFFFF 0x00000083
|
||||||
|
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||||
|
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||||
|
mask_write 0XF8006168 0x001FFFFF 0x00000124
|
||||||
|
mask_write 0XF800616C 0x001FFFFF 0x00000125
|
||||||
|
mask_write 0XF8006170 0x001FFFFF 0x00000112
|
||||||
|
mask_write 0XF8006174 0x001FFFFF 0x00000116
|
||||||
|
mask_write 0XF800617C 0x000FFFFF 0x000000C3
|
||||||
|
mask_write 0XF8006180 0x000FFFFF 0x000000C3
|
||||||
|
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||||
|
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||||
|
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||||
|
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||||
|
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||||
|
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||||
|
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||||
|
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||||
|
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||||
|
mask_poll 0XF8000B74 0x00002000
|
||||||
|
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||||
|
mask_poll 0XF8006054 0x00000007
|
||||||
|
}
|
||||||
|
proc ps7_mio_init_data_2_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||||
|
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||||
|
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||||
|
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||||
|
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||||
|
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B6C 0x00007FFF 0x00000209
|
||||||
|
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||||
|
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||||
|
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||||
|
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000704 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000708 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF800070C 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000710 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000714 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000718 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000720 0x00003FFF 0x00000700
|
||||||
|
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000740 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000744 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000748 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF800074C 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000750 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000754 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000758 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF800075C 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000760 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000764 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000768 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF800076C 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000770 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000774 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||||
|
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||||
|
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_peripherals_init_data_2_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||||
|
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||||
|
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||||
|
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||||
|
mask_write 0XE000D000 0x00080000 0x00080000
|
||||||
|
mask_write 0XF8007000 0x20000000 0x00000000
|
||||||
|
}
|
||||||
|
proc ps7_post_config_2_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||||
|
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_debug_2_0 {} {
|
||||||
|
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||||
|
}
|
||||||
|
proc ps7_pll_init_data_1_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||||
|
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||||
|
mask_write 0XF8000100 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000100 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000100 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000001
|
||||||
|
mask_write 0XF8000100 0x00000010 0x00000000
|
||||||
|
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||||
|
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||||
|
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||||
|
mask_write 0XF8000104 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000104 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000104 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000002
|
||||||
|
mask_write 0XF8000104 0x00000010 0x00000000
|
||||||
|
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||||
|
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||||
|
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||||
|
mask_write 0XF8000108 0x00000010 0x00000010
|
||||||
|
mask_write 0XF8000108 0x00000001 0x00000001
|
||||||
|
mask_write 0XF8000108 0x00000001 0x00000000
|
||||||
|
mask_poll 0XF800010C 0x00000004
|
||||||
|
mask_write 0XF8000108 0x00000010 0x00000000
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_clock_init_data_1_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||||
|
mask_write 0XF8000138 0x00000011 0x00000001
|
||||||
|
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||||
|
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||||
|
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||||
|
mask_write 0XF8000154 0x00003F33 0x00001402
|
||||||
|
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||||
|
mask_write 0XF8000170 0x03F03F30 0x00200400
|
||||||
|
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||||
|
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_ddr_init_data_1_0 {} {
|
||||||
|
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||||
|
mask_write 0XF8006004 0x1FFFFFFF 0x00081081
|
||||||
|
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||||
|
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||||
|
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||||
|
mask_write 0XF8006014 0x001FFFFF 0x0004159B
|
||||||
|
mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
|
||||||
|
mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
|
||||||
|
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||||
|
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||||
|
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||||
|
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||||
|
mask_write 0XF8006030 0xFFFFFFFF 0x00040930
|
||||||
|
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||||
|
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||||
|
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||||
|
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||||
|
mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
|
||||||
|
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||||
|
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||||
|
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||||
|
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||||
|
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||||
|
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||||
|
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||||
|
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||||
|
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||||
|
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||||
|
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||||
|
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||||
|
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||||
|
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||||
|
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||||
|
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||||
|
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||||
|
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||||
|
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||||
|
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||||
|
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||||
|
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||||
|
mask_write 0XF800612C 0x000FFFFF 0x00033C03
|
||||||
|
mask_write 0XF8006130 0x000FFFFF 0x00034003
|
||||||
|
mask_write 0XF8006134 0x000FFFFF 0x0002F400
|
||||||
|
mask_write 0XF8006138 0x000FFFFF 0x00030400
|
||||||
|
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||||
|
mask_write 0XF8006154 0x000FFFFF 0x00000083
|
||||||
|
mask_write 0XF8006158 0x000FFFFF 0x00000083
|
||||||
|
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||||
|
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||||
|
mask_write 0XF8006168 0x001FFFFF 0x00000124
|
||||||
|
mask_write 0XF800616C 0x001FFFFF 0x00000125
|
||||||
|
mask_write 0XF8006170 0x001FFFFF 0x00000112
|
||||||
|
mask_write 0XF8006174 0x001FFFFF 0x00000116
|
||||||
|
mask_write 0XF800617C 0x000FFFFF 0x000000C3
|
||||||
|
mask_write 0XF8006180 0x000FFFFF 0x000000C3
|
||||||
|
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||||
|
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||||
|
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||||
|
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||||
|
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||||
|
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||||
|
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||||
|
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||||
|
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||||
|
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||||
|
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||||
|
mask_poll 0XF8000B74 0x00002000
|
||||||
|
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||||
|
mask_poll 0XF8006054 0x00000007
|
||||||
|
}
|
||||||
|
proc ps7_mio_init_data_1_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||||
|
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||||
|
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||||
|
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||||
|
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||||
|
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||||
|
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||||
|
mask_write 0XF8000B6C 0x000073FF 0x00000209
|
||||||
|
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||||
|
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||||
|
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||||
|
mask_write 0XF8000700 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000704 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000708 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF800070C 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000710 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000714 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF8000718 0x00003FFF 0x00000702
|
||||||
|
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000720 0x00003FFF 0x00000700
|
||||||
|
mask_write 0XF8000724 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000728 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF800072C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000730 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000734 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000738 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF800073C 0x00003FFF 0x00000600
|
||||||
|
mask_write 0XF8000740 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000744 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000748 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF800074C 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000750 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000754 0x00003FFF 0x00000302
|
||||||
|
mask_write 0XF8000758 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF800075C 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000760 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000764 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000768 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF800076C 0x00003FFF 0x00000303
|
||||||
|
mask_write 0XF8000770 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000774 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000778 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800077C 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000780 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000784 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000788 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800078C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000790 0x00003FFF 0x00000305
|
||||||
|
mask_write 0XF8000794 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF8000798 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF800079C 0x00003FFF 0x00000304
|
||||||
|
mask_write 0XF80007A0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007A8 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007AC 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B0 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B4 0x00003FFF 0x00000380
|
||||||
|
mask_write 0XF80007B8 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007BC 0x00003F01 0x00000201
|
||||||
|
mask_write 0XF80007C0 0x00003FFF 0x000002E0
|
||||||
|
mask_write 0XF80007C4 0x00003FFF 0x000002E1
|
||||||
|
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||||
|
mask_write 0XF80007D0 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF80007D4 0x00003FFF 0x00000280
|
||||||
|
mask_write 0XF8000830 0x003F003F 0x002F002E
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_peripherals_init_data_1_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||||
|
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||||
|
mask_write 0XE0001018 0x0000FFFF 0x0000003E
|
||||||
|
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||||
|
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||||
|
mask_write 0XE000D000 0x00080000 0x00080000
|
||||||
|
mask_write 0XF8007000 0x20000000 0x00000000
|
||||||
|
}
|
||||||
|
proc ps7_post_config_1_0 {} {
|
||||||
|
mwr -force 0XF8000008 0x0000DF0D
|
||||||
|
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||||
|
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||||
|
mwr -force 0XF8000004 0x0000767B
|
||||||
|
}
|
||||||
|
proc ps7_debug_1_0 {} {
|
||||||
|
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||||
|
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||||
|
}
|
||||||
|
set PCW_SILICON_VER_1_0 "0x0"
|
||||||
|
set PCW_SILICON_VER_2_0 "0x1"
|
||||||
|
set PCW_SILICON_VER_3_0 "0x2"
|
||||||
|
set APU_FREQ 666666667
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
proc mask_poll { addr mask } {
|
||||||
|
set count 1
|
||||||
|
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||||
|
set maskedval [expr {$curval & $mask}]
|
||||||
|
while { $maskedval == 0 } {
|
||||||
|
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||||
|
set maskedval [expr {$curval & $mask}]
|
||||||
|
set count [ expr { $count + 1 } ]
|
||||||
|
if { $count == 100000000 } {
|
||||||
|
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||||
|
break
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
proc mask_delay { addr val } {
|
||||||
|
set delay [ get_number_of_cycles_for_delay $val ]
|
||||||
|
perf_reset_and_start_timer
|
||||||
|
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||||
|
set maskedval [expr {$curval < $delay}]
|
||||||
|
while { $maskedval == 1 } {
|
||||||
|
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||||
|
set maskedval [expr {$curval < $delay}]
|
||||||
|
}
|
||||||
|
perf_reset_clock
|
||||||
|
}
|
||||||
|
|
||||||
|
proc ps_version { } {
|
||||||
|
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||||
|
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||||
|
return $mask_sil_ver;
|
||||||
|
}
|
||||||
|
|
||||||
|
proc ps7_post_config {} {
|
||||||
|
|
||||||
|
ps7_post_config_1_0
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
proc ps7_debug {} {
|
||||||
|
ps7_debug_1_0
|
||||||
|
|
||||||
|
}
|
||||||
|
proc ps7_init {} {
|
||||||
|
|
||||||
|
ps7_mio_init_data_1_0
|
||||||
|
ps7_pll_init_data_1_0
|
||||||
|
ps7_clock_init_data_1_0
|
||||||
|
ps7_ddr_init_data_1_0
|
||||||
|
ps7_peripherals_init_data_1_0
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
# For delay calculation using global timer
|
||||||
|
|
||||||
|
# start timer
|
||||||
|
proc perf_start_clock { } {
|
||||||
|
|
||||||
|
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||||
|
|
||||||
|
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||||
|
}
|
||||||
|
|
||||||
|
# stop timer and reset timer count regs
|
||||||
|
proc perf_reset_clock { } {
|
||||||
|
perf_disable_clock
|
||||||
|
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||||
|
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||||
|
}
|
||||||
|
|
||||||
|
# Compute mask for given delay in miliseconds
|
||||||
|
proc get_number_of_cycles_for_delay { delay } {
|
||||||
|
|
||||||
|
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||||
|
variable APU_FREQ
|
||||||
|
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
# stop timer
|
||||||
|
proc perf_disable_clock {} {
|
||||||
|
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||||
|
}
|
||||||
|
|
||||||
|
proc perf_reset_and_start_timer {} {
|
||||||
|
perf_reset_clock
|
||||||
|
perf_start_clock
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
#
|
||||||
|
# TCL to allow the Xilinx PS7 Init TCL code to run in OpenOCD.
|
||||||
|
#
|
||||||
|
|
||||||
|
proc mrd { args } {
|
||||||
|
if {[llength $args] == 0} {
|
||||||
|
echo "mrd address \[count \[w|h|b\]\]"
|
||||||
|
echo " Read <count> memory locations starting at <address>. Defaults to one word."
|
||||||
|
return
|
||||||
|
}
|
||||||
|
set addr [lindex $args 0]
|
||||||
|
set count 1
|
||||||
|
set bits 32
|
||||||
|
if {[llength $args] > 1} {
|
||||||
|
set count [lindex $args 1]
|
||||||
|
if {[llength $args] > 2} {
|
||||||
|
switch [lindex $args 2] {
|
||||||
|
w { set bits 32 }
|
||||||
|
h { set bits 16 }
|
||||||
|
b { set bits 8 }
|
||||||
|
default { set bits 32 }
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
mem2array x $bits $addr $count
|
||||||
|
set nibbles [expr {$bits / 4}]
|
||||||
|
set bytes [expr {$bits / 8}]
|
||||||
|
set result {}
|
||||||
|
foreach {idx elmt} $x {
|
||||||
|
append result [format "%08x: %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt]
|
||||||
|
}
|
||||||
|
return $result
|
||||||
|
}
|
||||||
|
|
||||||
|
proc mwr { args } {
|
||||||
|
set addr [lindex $args 1]
|
||||||
|
set data [lindex $args 2]
|
||||||
|
mww $addr $data
|
||||||
|
}
|
||||||
|
|
||||||
|
proc mask_write { addr mask value } {
|
||||||
|
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||||
|
set maskedval [expr {$curval & ~$mask}]
|
||||||
|
#echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]"
|
||||||
|
set writeval(0) [expr {$maskedval | $value}]
|
||||||
|
#echo " $addr <= [format 0x%08x $writeval(0)] ([format 0x%08x $curval]: [format 0x%08x $mask]/[format 0x%08x $value])"
|
||||||
|
array2mem writeval 32 $addr 1
|
||||||
|
}
|
||||||
|
|
||||||
|
proc xilinx_ps7_init { } {
|
||||||
|
poll off
|
||||||
|
reset init
|
||||||
|
reset halt
|
||||||
|
targets zynq.cpu.0
|
||||||
|
sleep 100
|
||||||
|
halt
|
||||||
|
ps7_debug
|
||||||
|
ps7_init
|
||||||
|
ps7_post_config
|
||||||
|
poll on
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,42 @@
|
||||||
|
source ./digilent_jtag_smt2_nc.cfg
|
||||||
|
adapter_khz 10000
|
||||||
|
|
||||||
|
set PL_TAPID 0x03727093
|
||||||
|
set SMP 1
|
||||||
|
|
||||||
|
source ./zynq-7000.cfg
|
||||||
|
source ./xilinx-tcl.cfg
|
||||||
|
source ./ps7_init.tcl
|
||||||
|
|
||||||
|
reset_config srst_only srst_push_pull
|
||||||
|
|
||||||
|
set XC7_JSHUTDOWN 0x0d
|
||||||
|
set XC7_JPROGRAM 0x0b
|
||||||
|
set XC7_JSTART 0x0c
|
||||||
|
set XC7_BYPASS 0x3f
|
||||||
|
|
||||||
|
proc xc7_program {tap} {
|
||||||
|
global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
|
||||||
|
irscan $tap $XC7_JSHUTDOWN
|
||||||
|
irscan $tap $XC7_JPROGRAM
|
||||||
|
runtest 60000
|
||||||
|
#JSTART prevents this from working...
|
||||||
|
#irscan $tap $XC7_JSTART
|
||||||
|
runtest 2000
|
||||||
|
irscan $tap $XC7_BYPASS
|
||||||
|
runtest 2000
|
||||||
|
}
|
||||||
|
|
||||||
|
pld device virtex2 zynq.tap 1
|
||||||
|
init
|
||||||
|
xc7_program zynq.tap
|
||||||
|
|
||||||
|
xilinx_ps7_init
|
||||||
|
|
||||||
|
# Disable MMU
|
||||||
|
targets $_TARGETNAME_1
|
||||||
|
arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
|
||||||
|
targets $_TARGETNAME_0
|
||||||
|
arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,211 @@
|
||||||
|
#
|
||||||
|
# Xilinx Zynq 7000 SoC
|
||||||
|
#
|
||||||
|
# Chris Johns <chrisj@rtems.org>
|
||||||
|
#
|
||||||
|
# Setup
|
||||||
|
# -----
|
||||||
|
#
|
||||||
|
# Create a user configuration following the "Configuration Basics" in the user
|
||||||
|
# documentation. In the file have:
|
||||||
|
#
|
||||||
|
# source [find interface/ftdi/flyswatter2.cfg]
|
||||||
|
# source [find board/zynq-zc706-eval.cfg]
|
||||||
|
# adapter_khz 2000
|
||||||
|
# init
|
||||||
|
#
|
||||||
|
|
||||||
|
if { [info exists CHIPNAME] } {
|
||||||
|
global _CHIPNAME
|
||||||
|
set _CHIPNAME $CHIPNAME
|
||||||
|
} else {
|
||||||
|
global _CHIPNAME
|
||||||
|
set _CHIPNAME zynq
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [info exists ENDIAN] } {
|
||||||
|
set _ENDIAN $ENDIAN
|
||||||
|
} else {
|
||||||
|
# this defaults to a bigendian
|
||||||
|
set _ENDIAN little
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [info exists SMP] } {
|
||||||
|
global _SMP
|
||||||
|
set _SMP 1
|
||||||
|
} else {
|
||||||
|
global _SMP
|
||||||
|
set _SMP 0
|
||||||
|
}
|
||||||
|
|
||||||
|
#
|
||||||
|
# PL Tap.
|
||||||
|
#
|
||||||
|
# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
|
||||||
|
# 0x03731093 - ZC706 Eval board 1.1
|
||||||
|
# 0x23731093 - ??
|
||||||
|
# 0x23727093 - Zedboard Rev. C and D
|
||||||
|
#
|
||||||
|
# Set in your configuration file or board specific file.
|
||||||
|
#
|
||||||
|
if { [info exists PL_TAPID] } {
|
||||||
|
set _PL_TAPID $PL_TAPID
|
||||||
|
} else {
|
||||||
|
set _PL_TAPID 0x03731093
|
||||||
|
}
|
||||||
|
|
||||||
|
jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
|
||||||
|
-expected-id $_PL_TAPID
|
||||||
|
|
||||||
|
#
|
||||||
|
# CoreSight Debug Access Port
|
||||||
|
#
|
||||||
|
if { [info exists DAP_TAPID] } {
|
||||||
|
set _DAP_TAPID $DAP_TAPID
|
||||||
|
} else {
|
||||||
|
set _DAP_TAPID 0x4ba00477
|
||||||
|
}
|
||||||
|
|
||||||
|
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
|
||||||
|
-expected-id $_DAP_TAPID
|
||||||
|
|
||||||
|
#
|
||||||
|
# GDB target: Cortex-A9, using DAP, configuring only one core
|
||||||
|
# Base addresses of cores:
|
||||||
|
# core 0 - 0xF8890000
|
||||||
|
# core 1 - 0xF8892000
|
||||||
|
#
|
||||||
|
# Read from the ROM table with the patch to read the nested table.
|
||||||
|
#
|
||||||
|
|
||||||
|
set _TARGETNAME_0 $_CHIPNAME.cpu.0
|
||||||
|
set _TARGETNAME_1 $_CHIPNAME.cpu.1
|
||||||
|
|
||||||
|
target create $_TARGETNAME_0 cortex_a -coreid 0 \
|
||||||
|
-endian $_ENDIAN \
|
||||||
|
-chain-position $_CHIPNAME.dap \
|
||||||
|
-dbgbase 0x80090000
|
||||||
|
if { $_SMP } {
|
||||||
|
echo "Zynq CPU1."
|
||||||
|
target create $_TARGETNAME_1 cortex_a -coreid 1 \
|
||||||
|
-endian $_ENDIAN \
|
||||||
|
-chain-position $_CHIPNAME.dap \
|
||||||
|
-dbgbase 0x80092000
|
||||||
|
target smp $_TARGETNAME_0 $_TARGETNAME_1
|
||||||
|
}
|
||||||
|
|
||||||
|
#
|
||||||
|
# Hack to get the registers into a stable state when first booting a zynq in
|
||||||
|
# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
|
||||||
|
# register the write will fail because gdb attempts to scan or unwind the
|
||||||
|
# current frame and the bad address seems to lock the bus up. This code puts
|
||||||
|
# the registers into the OCM and hopefull safe.
|
||||||
|
#
|
||||||
|
proc zynq_clear_registers { target } {
|
||||||
|
echo "Zynq-7000 Series setup: $target"
|
||||||
|
set _OCM_END 0x0003FFF0
|
||||||
|
mww phys 0xF8007000 0x4E00E07F
|
||||||
|
reg r0 0
|
||||||
|
reg r1 0
|
||||||
|
reg r2 0
|
||||||
|
reg r3 0
|
||||||
|
reg r4 0
|
||||||
|
reg r5 0
|
||||||
|
reg r6 0
|
||||||
|
reg r7 0
|
||||||
|
reg r8 0
|
||||||
|
reg r9 0
|
||||||
|
reg r10 0
|
||||||
|
reg r11 $_OCM_END
|
||||||
|
reg sp_svc $_OCM_END
|
||||||
|
reg lr_svc $_OCM_END
|
||||||
|
reg sp_abt $_OCM_END
|
||||||
|
reg lr_abt $_OCM_END
|
||||||
|
reg sp_und $_OCM_END
|
||||||
|
reg lr_und $_OCM_END
|
||||||
|
}
|
||||||
|
|
||||||
|
proc zynq_disable_mmu_and_caches { target } {
|
||||||
|
# arm mcr pX op1 CRn CRm op2 value
|
||||||
|
echo "Disable MMU and caches"
|
||||||
|
# Invalidate caches
|
||||||
|
catch {
|
||||||
|
$target arm mcr 15 0 7 5 0 0
|
||||||
|
$target arm mcr 15 0 7 7 0 0
|
||||||
|
# Invalidate all TLBs
|
||||||
|
$target arm mcr 15 0 8 5 0 0
|
||||||
|
$target arm mcr 15 0 8 6 0 0
|
||||||
|
$target arm mcr 15 0 8 7 0 0
|
||||||
|
$target arm mcr 15 4 8 3 0 0
|
||||||
|
$target arm mcr 15 4 8 7 0 0
|
||||||
|
set cp [$target arm mrc 15 0 1 0 0]
|
||||||
|
echo "SCTRL => [format 0x%x $cp]"
|
||||||
|
set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
|
||||||
|
set cp [expr ($cp & ~$mask)]
|
||||||
|
$target arm mcr 15 0 1 0 0 $cp
|
||||||
|
echo "SCTRL <= [format 0x%x $cp]"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc zynq_boot_ocm_setup { } {
|
||||||
|
#
|
||||||
|
# Enable the OCM
|
||||||
|
#
|
||||||
|
echo "Zynq Boot OCM setup"
|
||||||
|
catch {
|
||||||
|
mww phys 0xF8000008 0xDF0D
|
||||||
|
mww phys 0xF8000238 0
|
||||||
|
mww phys 0xF8000910 0xC
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc zynq_rtems_setup { } {
|
||||||
|
cache_config l2x 0xF8F02000 8
|
||||||
|
cortex_a maskisr on
|
||||||
|
}
|
||||||
|
|
||||||
|
proc zynq_restart { wait } {
|
||||||
|
global _SMP
|
||||||
|
global _TARGETNAME_0
|
||||||
|
global _TARGETNAME_1
|
||||||
|
set target0 $_TARGETNAME_0
|
||||||
|
set target1 $_TARGETNAME_1
|
||||||
|
echo "Zynq reset, resetting the board ... "
|
||||||
|
poll off
|
||||||
|
#
|
||||||
|
# Issue the reset via the SLCR
|
||||||
|
#
|
||||||
|
catch {
|
||||||
|
mww phys 0xF8000008 0xDF0D
|
||||||
|
mww phys 0xF8000200 1
|
||||||
|
}
|
||||||
|
echo "Zynq reset waiting for $wait msecs ... "
|
||||||
|
sleep $wait
|
||||||
|
#
|
||||||
|
# Reconnect the DAP etc due to the reset.
|
||||||
|
#
|
||||||
|
$target0 cortex_a dbginit
|
||||||
|
$target0 arm core_state arm
|
||||||
|
if { $_SMP } {
|
||||||
|
$target1 arm core_state arm
|
||||||
|
$target1 cortex_a dbginit
|
||||||
|
cortex_a smp_off
|
||||||
|
}
|
||||||
|
poll on
|
||||||
|
#
|
||||||
|
# We can now halt the core.
|
||||||
|
#
|
||||||
|
if { $_SMP } {
|
||||||
|
targets $target1
|
||||||
|
halt
|
||||||
|
}
|
||||||
|
targets $target0
|
||||||
|
halt
|
||||||
|
zynq_rtems_setup
|
||||||
|
}
|
||||||
|
|
||||||
|
proc zynq_gdb_attach { target } {
|
||||||
|
catch {
|
||||||
|
halt
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue