2019-05-05 20:56:23 +08:00
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#![no_std]
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#![no_main]
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#![feature(asm)]
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2019-05-31 02:30:19 +08:00
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#![feature(global_asm)]
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2019-05-05 20:56:23 +08:00
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#![feature(naked_functions)]
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2019-06-09 07:00:58 +08:00
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#![feature(compiler_builtins_lib)]
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2019-06-17 09:32:10 +08:00
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#![feature(never_type)]
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2019-10-31 08:41:10 +08:00
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#![feature(alloc_error_handler)]
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2019-08-11 06:55:27 +08:00
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// TODO: disallow unused/dead_code when code moves into a lib crate
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#![allow(dead_code)]
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2019-05-05 20:56:23 +08:00
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2019-11-01 02:20:49 +08:00
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extern crate alloc;
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2019-11-11 09:37:06 +08:00
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use alloc::{vec, vec::Vec};
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2019-11-11 08:21:30 +08:00
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use core::mem::transmute;
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2019-05-05 20:56:23 +08:00
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use r0::zero_bss;
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2019-06-09 07:00:58 +08:00
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use compiler_builtins as _;
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2019-07-05 06:44:53 +08:00
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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2019-11-11 08:21:30 +08:00
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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2019-07-05 06:44:53 +08:00
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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2019-05-05 20:56:23 +08:00
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2019-05-07 05:56:53 +08:00
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mod regs;
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2019-05-05 20:56:23 +08:00
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mod cortex_a9;
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2019-11-11 09:37:06 +08:00
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mod abort;
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mod panic;
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2019-10-19 05:46:00 +08:00
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mod zynq;
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2019-11-11 09:37:06 +08:00
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mod stdio;
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mod ram;
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2019-05-05 20:56:23 +08:00
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2019-06-12 06:20:23 +08:00
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use crate::regs::{RegisterR, RegisterW};
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2019-06-17 09:32:10 +08:00
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use crate::cortex_a9::{asm, regs::*, mmu};
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2019-05-24 01:05:06 +08:00
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2019-05-05 20:56:23 +08:00
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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2019-05-27 07:44:24 +08:00
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static mut __stack_start: u32;
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2019-05-05 20:56:23 +08:00
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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2019-06-12 06:20:23 +08:00
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match MPIDR.read() & CORE_MASK {
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2019-05-05 20:56:23 +08:00
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0 => {
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2019-06-12 06:20:23 +08:00
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SP.write(&mut __stack_start as *mut _ as u32);
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2019-05-20 07:21:22 +08:00
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boot_core0();
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2019-05-05 20:56:23 +08:00
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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2019-05-30 08:41:44 +08:00
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#[naked]
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#[inline(never)]
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2019-05-20 07:21:22 +08:00
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unsafe fn boot_core0() -> ! {
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2019-05-24 01:05:06 +08:00
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l1_cache_init();
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2019-05-20 07:21:22 +08:00
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zero_bss(&mut __bss_start, &mut __bss_end);
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2019-05-30 08:41:44 +08:00
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2019-06-18 08:22:07 +08:00
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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2019-06-17 09:32:10 +08:00
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main();
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panic!("return from main");
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});
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2019-05-20 07:21:22 +08:00
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}
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2019-05-24 01:05:06 +08:00
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fn l1_cache_init() {
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2019-10-18 06:11:51 +08:00
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use crate::cortex_a9::cache::*;
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2019-05-24 01:05:06 +08:00
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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2019-10-18 06:11:51 +08:00
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//
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// NOTE: It is both faster and correct to only invalidate instead
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// of also flush the cache (as was done before with
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// `dccisw()`) and it is correct to perform this operation
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// for all of the L1 data cache rather than a (previously
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// unspecified) combination of one cache set and one cache
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// way.
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dciall();
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2019-05-24 01:05:06 +08:00
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}
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2019-07-05 06:44:53 +08:00
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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2019-05-05 20:56:23 +08:00
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fn main() {
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2019-06-20 06:30:18 +08:00
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println!("Main.");
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2019-10-22 04:19:03 +08:00
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2019-10-26 05:19:34 +08:00
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let mut ddr = zynq::ddr::DdrRam::new();
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println!("DDR: {:?}", ddr.status());
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ddr.memtest();
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2019-11-11 09:37:06 +08:00
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ram::init_alloc(&mut ddr);
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2019-10-31 08:41:10 +08:00
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2019-10-22 04:19:03 +08:00
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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2019-06-20 06:30:18 +08:00
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println!("Eth on");
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2019-05-08 01:28:33 +08:00
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2019-11-01 02:20:49 +08:00
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const RX_LEN: usize = 8;
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let mut rx_descs = (0..RX_LEN)
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.map(|_| zynq::eth::rx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut rx_buffers = vec![[0u8; zynq::eth::MTU]; RX_LEN];
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2019-09-29 07:39:57 +08:00
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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2019-11-01 02:20:49 +08:00
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const TX_LEN: usize = 8;
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let mut tx_descs = (0..TX_LEN)
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.map(|_| zynq::eth::tx::DescEntry::zeroed())
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.collect::<Vec<_>>();
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let mut tx_buffers = vec![[0u8; zynq::eth::MTU]; TX_LEN];
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2019-08-11 06:55:27 +08:00
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let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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2019-07-05 06:44:53 +08:00
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//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
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let mut eth = eth.start_tx(
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// HACK
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2019-11-01 02:20:49 +08:00
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unsafe { transmute(tx_descs.as_mut_slice()) },
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unsafe { transmute(tx_buffers.as_mut_slice()) },
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2019-07-05 06:44:53 +08:00
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);
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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2019-11-11 08:04:55 +08:00
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let local_addr = IpAddress::v4(192, 168, 1, 28);
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2019-07-05 06:44:53 +08:00
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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2019-11-01 02:20:49 +08:00
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let mut neighbor_storage = vec![None; 256];
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2019-07-05 06:44:53 +08:00
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let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.neighbor_cache(neighbor_cache)
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.finalize();
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let mut sockets_storage = [
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None, None, None, None,
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None, None, None, None
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];
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let mut sockets = SocketSet::new(&mut sockets_storage[..]);
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let mut time = 0u32;
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2019-06-10 08:44:29 +08:00
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loop {
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2019-07-05 06:44:53 +08:00
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time += 1;
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2019-11-11 08:21:30 +08:00
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let timestamp = Instant::from_millis(time);
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2019-07-05 06:44:53 +08:00
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match iface.poll(&mut sockets, timestamp) {
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Ok(_) => {},
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2019-06-22 07:20:18 +08:00
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Err(e) => {
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2019-07-05 06:44:53 +08:00
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println!("poll error: {}", e);
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2019-06-10 08:44:29 +08:00
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}
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}
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2019-06-22 07:34:47 +08:00
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2019-07-05 06:44:53 +08:00
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// match eth.recv_next() {
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// Ok(Some(pkt)) => {
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// print!("eth: rx {} bytes", pkt.len());
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// for b in pkt.iter() {
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// print!(" {:02X}", b);
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// }
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// println!("");
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// }
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// Ok(None) => {}
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// Err(e) => {
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// println!("eth rx error: {:?}", e);
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// }
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// }
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// match eth.send(512) {
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// Some(mut pkt) => {
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// let mut x = 0;
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// for b in pkt.iter_mut() {
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// *b = x;
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// x += 1;
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// }
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// println!("eth tx {} bytes", pkt.len());
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// }
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// None => println!("eth tx shortage"),
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// }
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2019-06-10 08:44:29 +08:00
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}
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2019-05-28 06:28:35 +08:00
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}
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2019-05-31 02:30:19 +08:00
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