forked from M-Labs/nix-scripts
Sebastien Bourdeauducq
fcc91513ec
This is becoming too complicated, and with the number of systems increasing we should find a better way of managing bitstream builds anyway. Simply caching Verilog->bitfile does not cut it. |
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| .. | ||
| artiq.json | ||
| mcu.json | ||
| web.json | ||