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architeuthis c3a87290ce 5432: spellcheck, style 2024-11-17 20:42:11 +01:00
architeuthis 49c06af717 4410-4412: replace dead link 2024-11-16 10:44:21 +08:00
architeuthis bebd7bbfda 4456: spellcheck, style 2024-11-16 10:44:21 +08:00
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architeuthis 480e8b2966 preamble: codesection add heading 2024-11-16 10:43:46 +08:00
architeuthis b9b103b38e 2118-2128, 2245: fixes 2024-11-16 10:43:46 +08:00
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architeuthidae 5acedc8f40 2118-2128: spellcheck, style 2024-11-16 10:43:46 +08:00
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5
1124.tex
View File

@ -277,10 +277,7 @@ Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on th
\newpage
\section{Example ARTIQ Code}
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources on the Kasli 2.0 1124 carrier board. They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material on the functions and structures used here.
\codesection{Kasli 2.0 1124 carrier}
\subsection{Direct Memory Access (DMA)}
Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.

294
2118-2128.tex
View File

@ -1,5 +1,5 @@
\include{preamble.tex}
\graphicspath{{images}}
\input{preamble.tex}
\graphicspath{{images/2118-2128}{images}}
\title{2118 BNC-TTL / 2128 SMA-TTL}
\author{M-Labs Limited}
@ -13,31 +13,30 @@
\section{Features}
\begin{itemize}
\item{8 channels.}
\item{Input and output capable.}
\item{Galvanically isolated.}
\item{3ns minimum pulse width.}
\item{BNC or SMA connectors.}
\item{8 TTL channels}
\item{Input- and output-capable}
\item{Galvanically isolated}
\item{3ns minimum pulse width}
\item{BNC or SMA connectors}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\end{itemize}
\section{General Description}
The 2118 BNC-TTL card is a 8hp EEM module, while the 2128 SMA-TTL card is a 4hp EEM module.
Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides two banks of four digital channels each, with BNC (2118) or SMA (2128) connectors.
Each bank has individual ground isolation.
The direction (input or output) of each bank can be selected using DIP switches.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
Outputs tolerate short circuits indefinitely.
The card support a minimum pulse width of 3ns.
The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely.
Both cards are capable of a minimum pulse width of 3ns.
% Switch to next column
\vfill\break
@ -89,8 +88,6 @@ The card support a minimum pulse width of 3ns.
\draw (0,0) circle(0.8);
\end{scope}
\draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
\draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
@ -113,22 +110,22 @@ The card support a minimum pulse width of 3ns.
\begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\end{scope}
@ -137,12 +134,12 @@ The card support a minimum pulse width of 3ns.
\begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\draw (0.8,-3.05) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
@ -151,22 +148,22 @@ The card support a minimum pulse width of 3ns.
\begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% channel 5,6,7,8
@ -297,47 +294,41 @@ The card support a minimum pulse width of 3ns.
\begin{figure}[hbt!]
\centering
\subfloat[\centering BNC-TTL]{{
\includegraphics[height=1.8in]{2118-2128/DIO_BNC_FP.jpg}
\includegraphics[height=1.8in]{2118-2128/photo2118.jpg}
}}%
\subfloat[\centering SMA-TTL]{{
\includegraphics[height=1.8in]{2118-2128/DIO_SMA_FP.jpg}
\includegraphics[height=1.8in]{2118-2128/photo2128.jpg}
}}%
\caption{BNC-TTL/SMA-TTL Card photos}%
\includegraphics[height=1.8in]{photo2118-2128.jpg }
\caption{BNC-TTL and SMA-TTL cards}%
\includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
\caption{BNC-TTL and SMA-TTL front panels}%
\label{fig:example}%
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
\section{Electrical Specifications}
All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
Specifications are based on the bus transceivers IC (SN74BCT25245DW\footnote{\label{transceiver}https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf})
and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}).
The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}https://github.com/sinara-hw/sinara/issues/187}.
Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level input voltage\repeatfootnote{transceiver} & $V_{IH}$ & 2 & & 5.5* & V & \\
High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
\hline
Low-level input voltage\repeatfootnote{transceiver} & $V_{IL}$ & -0.5 & & 0.8 & V & \\
Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
\hline
Input clamp current\repeatfootnote{transceiver} & $I_{OH}$ & & & -18 & mA & termination disabled \\
Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
\hline
High-level output current\repeatfootnote{transceiver} & $I_{OH}$ & & & -160 & mA & \\
High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
\hline
Low-level output current\repeatfootnote{transceiver} & $I_{OL}$ & & & 376 & mA & \\
Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
\thickhline
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
@ -345,185 +336,69 @@ The typical value of minimum pulse width is based on test results\footnote{\labe
\begin{table}[h]
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
High-level output voltage\repeatfootnote{transceiver} & $V_{OH}$ & 2 & & & V & $I_{OH}$=-160mA \\
& & 2.7 & & & V & $I_{OH}$=-6mA \\
High-level output voltage\repeatfootnote{transceiver} & 2 & & & V & $I_{OH}$=-160mA \\
& 2.7 & & & V & $I_{OH}$=-6mA \\
\hline
Low-level output voltage\repeatfootnote{transceiver} & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
& & & & 0.7 & V & $I_{OL}$=376mA \\
Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
& & & 0.7 & V & $I_{OL}$=376mA \\
\hline
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & & 3 & 5 & ns & \\
Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
\hline
Pulse width distortion\repeatfootnote{isolator} & $PWD$ & & 0.2 & 4.5 & ns & \\
Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns & \\
\hline
Peak jitter\repeatfootnote{isolator} & $T_{JIT(PK)}$ & & 350 & & ps & \\
Peak jitter\repeatfootnote{isolator} & & 350 & & ps & \\
\hline
Data rate\repeatfootnote{isolator} & & 0 & & 150 & Mbps & \\
Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\newpage
Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
Minimum pulse width was measured\repeatfootnote{sinara187}.
Pulses were generated from a DDS generator as an input of a BNC-TTL card.
The input BNC-TTL card is connected to another BNC-TTL card as an output.
The output signal is measured and shown.
\begin{figure}[h]
\begin{figure}[ht]
\centering
\includegraphics[height=3in]{2118-2128/bnc_ttl_min_pulse_width.png}
\includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
\caption{Minimum pulse width required for BNC-TTL card}
\label{fig:pulsewidth}
\end{figure}
The red trace refers to the input pulses from the DDS generator, while the blue trace is the measured signal from the output BNC-TTL card.
Note that the first input (red) pulse could not propagate through the signal chain.
The first output (blue) pulse is the result of the second input (red, 3ns width) pulse.
\newpage
\section{Front Panel Drawings}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_drawings.pdf}
\captionof{figure}{2118 BNC-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=2.8in]{2118-2128/bnc_ttl_assembly.pdf}
\captionof{figure}{2118 BNC-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90560220 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2118 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90457987 & 4 & CSCR M2.5*12.3 PAN PHL SS \\ \hline
2 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
3 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
4 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
5 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
6 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
7 & 3207076 & 0.01 & SCR M2.5*16 PAN 100 21101-222 \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
10 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT(100PCS) \\ \hline
11 & 90560220 & 1 & FP-LYKJ 3U8HP PANEL \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{2118-2128/sma_ttl_drawings.pdf}
\captionof{figure}{2128 SMA-TTL front panel drawings}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{2118-2128/sma_ttl_assembly.pdf}
\captionof{figure}{2128 SMA-TTL front panel assembly}
\end{center}
\end{multicols}
\begin{multicols}{2}
\begin{center}
\captionof{table}{Bill of Material (2128 Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\captionof{table}{Bill of Material (2128 Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90531967 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3001012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
6 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
7 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
8 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end{tabular}
\end{center}
\end{multicols}
The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly.
\section{Configuring IO Direction \& Termination}
The termination and IO direction can be configured by switches.
The per-channel termination and per-bank IO direction switches are found at the middle-left and middle-right of both cards respectively.
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank.
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item Closed switch (ON) \\
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\end{itemize}
\begin{figure}[hbt!]
\centering
\subfloat[\centering BNC-TTL]{{
\includegraphics[height=1.5in]{2118-2128/bnc_ttl_switches.jpg}
\includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
}}%
\subfloat[\centering SMA-TTL]{{
\includegraphics[height=1.5in]{2118-2128/sma_ttl_switches.jpg}
\includegraphics[height=1.5in]{sma_ttl_switches.jpg}
}}%
\caption{Position of switches}%
\end{figure}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2118 BNC-TTL/2128 SMA-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
@ -535,15 +410,13 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\newpage
\subsection{Sub-coarse-RTIO-cycle pulse}
With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
The TTL pulse must satisfy the minimum pulse width stated in the electircal specifications.
With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
\subsection{Edge counting in a 1ms window}
The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
The channel should be configured as input in both the gateware and hardware. Invoke one of the 3 methods to start edge detection.
The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
@ -551,41 +424,34 @@ The detected edges are registered to the RTIO input FIFO. By default, the FIFO c
Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
The RTIO system can report at most 1 edge detection event for every coarse RTIO cycle.
For example, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is 1 coarse RTIO cycle (typically 8 ns) with consideration of the RTIO specification alone.
However, both the electircal specifications and the possibility of triggering \texttt{RTIOOverflow} should be considered.
The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
\newpage
\subsection{Edge counting using \texttt{EdgeCounter}}
This example code uses the gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second.
If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle.
Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
\subsection{Responding to an external trigger}
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
\subsection{62.5 MHz clock signal generation}
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
\newpage
\subsection{Minimum Sustained Event Separation}
The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\subsection{Minimum sustained event separation}
The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
\begin{center}
\begin{table}[H]
\captionof{table}{Minimum sustained event separation of different carrier}
\captionof{table}{Minimum sustained event separation of different carriers}
\centering
\begin{tabular}{|c|c|c|}
\hline
@ -595,12 +461,8 @@ The following \texttt{run()} function finds the separation by approximating the
\end{table}
\end{center}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{2118 BNC-TTL/2128 SMA-TTL}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

154
2238.tex
View File

@ -1,5 +1,6 @@
\include{preamble.tex}
\input{preamble.tex}
\graphicspath{{images/2238}{images}}
\title{2238 MCX-TTL}
\author{M-Labs Limited}
\date{January 2022}
@ -12,31 +13,28 @@
\section{Features}
\begin{itemize}
\item{16 channels.}
\item{Input and output capable.}
\item{No galvanic isolation.}
\item{High speed and low jitter.}
\item{MCX connectors.}
\item{16 MCX-TTL channels}
\item{Input and output capable}
\item{No galvanic isolation}
\item{High speed and low jitter}
\item{MCX connectors}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\end{itemize}
\section{General Description}
The 2238 MCX-TTL card is a 4hp EEM module.
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides four banks of four digital channels each, with MCX connectors, controlled through 2 EEM connectors.
Each EEM connector controls two banks independently.
Single EEM operation is possible.
The direction (input or output) of each bank can be selected using DIP switches.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
% Switch to next column
\vfill\break
@ -222,22 +220,22 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{scope}[xshift=1.8cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=2.0cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=2.1cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% Bus transceiver 1
@ -245,22 +243,22 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{scope}[xshift=1.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.7cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.8cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% Bus transceiver 2
@ -268,22 +266,22 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{scope}[xshift=1.8cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=2cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=2.1cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% Bus transceiver 3
@ -291,22 +289,22 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{scope}[xshift=1.6cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.7cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.8cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=1.9cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% Connection termination switches to each IO line
@ -373,22 +371,22 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{scope}[xshift=5.3cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=5.4cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=5.5cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
\begin{scope}[xshift=5.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
\draw (0.4,0) to[short,-o](0.75,0);
\draw (0.78,0)-- +(30:0.46);
\draw (1.25,0)to[short,o-](1.6,0) ;
\draw (1.25,0)to[short,o-](1.6,0);
\end{scope}
% EEM Ports
@ -439,65 +437,66 @@ This card can achieve higher speed and lower jitter than the isolated 2118/2128
\begin{figure}[hbt!]
\centering
\includegraphics[height=1.8in]{DIO_MCX_FP.pdf}
\includegraphics[height=2in]{photo2238.jpg}
\caption{MCX-TTL Card photo}
\caption{MCX-TTL card}
\includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
\caption{MCX-TTL front panel}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{2238 MCX-TTL}{https://github.com/sinara-hw/DIO_MCX/wiki}
\section{Electrical Specifications}
Both recommended operating conditions and electrical characteristics are based on the datasheet of the bus transceivers IC (74LVT162245MTD\footnote{\label{transceiver}https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}).
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
\begin{table}[h]
\begin{threeparttable}
\caption{Recommended Operating Conditions}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Input voltage & $V_{I}$ & 0 & & 5.5* & V \\
Input voltage & 0 & & 5.5* & V \\
\hline
High-level output current & $I_{OH}$ & & & -24 & mA \\
High-level output current & & & -24 & mA \\
\hline
Low-level output current & $I_{OL}$ & & & 24 & mA \\
Low-level output current & & & 24 & mA \\
\hline
Input edge rate & $\frac{\Delta t}{\Delta V}$ & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
\thickhline
\multicolumn{7}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
\end{tabularx}
\end{threeparttable}
\end{table}
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
All specifications are in the recommended operating temperature range unless otherwise noted.
\begin{table}[h]
\begin{threeparttable}
\caption{Electrical Characteristics}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Input clamp diode voltage & $V_{IK}$ & & & -1.2 & V & $I_I =-36 mA$ \\
Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
\hline
Input high voltage & $V_{IH}$ & 2.0 & & & V & \\
Input high voltage & 2.0 & & & V & \\
\hline
Input low voltage & $V_{IL}$ & & & 0.8 & V & \\
Input low voltage & & & 0.8 & V & \\
\hline
Output high voltage & $V_{OH}$ & 2.0 & & & V & $I_{OH}=-24mA$ \\
& & 3.1 & & & V & $I_{OH}=-200\mu A$ \\
Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
& 3.1 & & & V & $I_{OH}=-200\mu A$ \\
\hline
Output low voltage & $V_{OL}$ & & & 0.8 & V & $I_{OL}=-24mA$ \\
& & & & 0.2 & V & $I_{OL}=-200\mu A$ \\
Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
& & & 0.2 & V & $I_{OL}=-200\mu A$ \\
\hline
Input current & $I_I$ & & & 20 & \textmu A & $V_I=5.5V$ \\
& & & & 2 & \textmu A & $V_I=3.3V$ \\
& & & & -10 & \textmu A & $V_I=0V$ \\
Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
& & & 2 & \textmu A & $V_I=3.3V$ \\
& & & -10 & \textmu A & $V_I=0V$ \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -506,18 +505,16 @@ All specifications are in the recommended operating temperature range unless oth
\newpage
\section{Configuring IO Direction \& Termination}
The termination and IO direction can be configured by switches.
The per-channel termination and per-bank IO direction switches are found at the top and middle of the card respectively.
IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
\begin{multicols}{2}
Termination switches selects the termination of each channel, between high impedence (OFF) and 50\textOmega~(ON).
Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
IO direction switches partly decides the IO direction of each bank.
\begin{itemize}
\itemsep0em
\item Closed switch (ON) \\
Fix the corresponding bank to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\end{itemize}
\columnbreak
\begin{center}
@ -528,12 +525,9 @@ IO direction switches partly decides the IO direction of each bank.
\end{multicols}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\codesection{2238 MCX-TTL card}
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
@ -544,8 +538,8 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
\newpage
\subsection{Counting rising edges in a 1ms window}
The channel should be configured as input in both the gateware and hardware.
\subsection{Edge counting in an 1ms window}
The channel should be configured as input in both gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
@ -556,12 +550,8 @@ If the gateware counter is enabled on the TTL channel, it can typically count up
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2238 MCX-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{2238 MCX-TTL}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

156
2245.tex
View File

@ -1,4 +1,4 @@
\include{preamble.tex}
\input{preamble.tex}
\graphicspath{{images/2245}{images}}
\usepackage{tikz-timing}
@ -16,35 +16,28 @@
\section{Features}
\begin{itemize}
\item{16 LVDS channels.}
\item{Input and output capable.}
\item{No galvanic isolation.}
\item{High speed and low jitter.}
\item{RJ45 connectors.}
\item{16 LVDS-TTL channels.}
\item{Input- and output-capable}
\item{No galvanic isolation}
\item{High speed and low jitter}
\item{RJ45 connectors}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Photon counting.}
\item{External equipment trigger.}
\item{Optical shutter control.}
\item{Serial communication to remote devices.}
\item{Photon counting}
\item{External equipment trigger}
\item{Optical shutter control}
\item{Serial communication with remote devices}
\end{itemize}
\section{General Description}
The 2245 LVDS-TTL card is a 4hp EEM module.
It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
Each card provides sixteen digital channels each, controlled through 2 EEM connectors.
Each EEM connector controls eight channels independently.
Single EEM operation is possible.
Each RJ45 connector exposes four digital channels in the LVDS format.
The direction (input or output) of each channel can be selected using DIP switches.
Outputs are intended to drive 100\textOmega~loads, inputs are 100\textOmega~terminated.
This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
Only shielded Ethernet Cat-6 cables should be connected.
Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
% Switch to next column
\vfill\break
@ -303,9 +296,9 @@ Only shielded Ethernet Cat-6 cables should be connected.
\begin{figure}[hbt!]
\centering
\includegraphics[height=2.1in]{DIO_RJ45_FP.pdf}
\includegraphics[height=2.1in]{photo2245.jpg}
\caption{LVDS-TTL Card photo}
\includegraphics[angle=90, height=1.7in]{photo2245.jpg}
\includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
\caption{LVDS-TTL card and front panel}
\end{figure}
@ -313,9 +306,11 @@ Only shielded Ethernet Cat-6 cables should be connected.
% page-by-page.
\onecolumn
\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
\section{Electrical Specifications}
Information in this section is based on the datasheet of the repeaters IC (FIN1101K8X\footnote{\label{repeaters}https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}).
All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
\begin{table}[h]
\begin{threeparttable}
@ -336,9 +331,7 @@ Information in this section is based on the datasheet of the repeaters IC (FIN11
\end{tabularx}
\end{threeparttable}
\end{table}
The recommended operating temperature is $-40\degree C \leq T_A \leq 85\degree C$.
All specifications are in the recommended operating temperature range unless otherwise noted.
All typical values of DC specifications are at $T_A = 25\degree C$.
\begin{table}[h]
@ -349,7 +342,7 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Output differentiual Voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
\cline{0-5}
$|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
\cline{0-5}
@ -359,7 +352,35 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\hline
Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
\hline
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended Input Voltage \\
Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
\begin{table}[h]
\begin{threeparttable}
\caption{AC Specifications}
\begin{tabularx}{\textwidth}{l | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
(20\% to 80\%) & & & & & \\
\cline{0-5}
Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
(80\% to 20\%) & & & & & \\
\cline{0-5}
Pulse width distortion & & 0.01 & 0.2 & ns & \\
\hline
LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
deterministic & & & & & 800 Mbps\\
\hline
LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
random (RMS) & & & & & \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -367,46 +388,18 @@ All typical values of DC specifications are at $T_A = 25\degree C$.
\newpage
All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise specified.
\begin{table}[h]
\begin{threeparttable}
\caption{AC Specifications}
\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
\thickhline
\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
\textbf{Unit} & \textbf{Conditions} \\
\hline
Differential Output Rise Time & \multirow{2}{*}{$t_{TLHD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & duty Cycle = 50\%.\\
(20\% to 80\%) & & & & & & \\
\cline{0-5}
Differential Output Fall Time & \multirow{2}{*}{$t_{THLD}$} & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
(80\% to 20\%) & & & & & & \\
\cline{0-5}
Pulse width distortion & $PWD$ & & 0.01 & 0.2 & ns & \\
\hline
LVDS data jitter, & \multirow{2}{*}{$t_{DJ}$} & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
deterministic & & & & & & 800 Mbps\\
\hline
LVDS clock jitter, & \multirow{2}{*}{$t_{RJ}$} & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
random (RMS) & & & & & & \\
\thickhline
\end{tabularx}
\end{threeparttable}
\end{table}
\section{Configuring IO Direction \& Termination}
The IO direction can be configured by switches, which are found at the top of the card.
\begin{multicols}{2}
IO direction switches partly decides the IO direction of each bank.
The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
\begin{itemize}
\itemsep0em
\item Closed switch (ON) \\
Fix the corresponding channel to output. The direction cannot be changed by I\textsuperscript{2}C.
\item Opened switch (OFF) \\
Switch to input mode. The direction is input by default. Configurable by I\textsuperscript{2}C.
\item IO direction switch closed (\texttt{ON}) \\
Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
\item IO direction switch open (OFF) \\
The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
\end{itemize}
\columnbreak
\vspace*{\fill}\columnbreak
\begin{center}
\centering
\includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
@ -416,15 +409,12 @@ IO direction switches partly decides the IO direction of each bank.
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 2245 LVDS-TTL card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\codesection{2245 LVDS-TTL card}
Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
\subsection{One pulse per second}
The channel should be configured as output in both the gateware and hardware.
The channel should be configured as output in both gateware and hardware.
\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
\subsection{Morse code}
@ -433,7 +423,7 @@ This example demonstrates some basic algorithmic features of the ARTIQ-Python la
\newpage
\subsection{Counting rising edges in a 1ms window}
The channel should be configured as input in both the gateware and hardware.
The channel should be configured as input in both gateware and hardware.
\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
@ -459,8 +449,7 @@ One channel needs to be configured as input, and the other as output.
\newpage
\subsection{SPI Master Device}
If a EEM port is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices.
Invocation of an SPI transfer follows this pattern:
If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
\begin{enumerate}
% The config register can be set using set_config.
% However, the only difference between these 2 methods is that set_config accepts an arbitrary
@ -493,7 +482,7 @@ The list of configurations supported in the gateware are listed as below:
\end{tabular}
\end{table}
The following ARTIQ example demonstrates the flow of an SPI transcation with a typical SPI setup with 3 homogeneous slaves.
The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
\begin{center}
\begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
@ -572,19 +561,16 @@ The following examples will assume the SPI communication has the following prope
\item Most significant bit (MSB) first
\item Full duplex
\end{itemize}
The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
\subsubsection{SPI frequency}
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
\subsubsection{SPI write}
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
Suppose the instruction and data are 8 bits and 32 bits respectively.
The timing diagram of such write operation is shown in the following.
Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
\begin{center}
\begin{tikztimingtable}
@ -605,11 +591,11 @@ The timing diagram of such write operation is shown in the following.
\end{center}
\newpage
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
\subsubsection{SPI read}
A 32-bits read is represented by the following timing diagram.
A 32-bit read is represented by the following timing diagram:
\begin{center}
\begin{tikztimingtable}
@ -634,12 +620,8 @@ Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This S
\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
\newpage
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2245 LVDS-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{2245 LVDS-TTL}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

236
4410-4412.tex
View File

@ -1,4 +1,4 @@
\include{preamble.tex}
\input{preamble.tex}
\graphicspath{{images/4410-4412}{images}}
\title{4410/4412 DDS Urukul}
@ -13,33 +13,28 @@
\section{Features}
\begin{itemize}
\item{4-channel 1GS/s DDS.}
\item{Output frequency ranges from \textless 1 to \textgreater 400 MHz.}
\item{Sub-Hz frequency resolution.}
\item{Controlled phase steps.}
\item{Accurate output amplitude control.}
\item{4-channel 1GS/s DDS}
\item{Output frequency from \textless 1 to \textgreater 400 MHz}
\item{Sub-Hz frequency resolution}
\item{Controlled phase steps}
\item{Accurate output amplitude control}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Dynamic low-noise RF source.}
\item{Driving RF electrodes in ion traps.}
\item{Driving acousto-optic modulators.}
\item{Form a laser intensity servo with 5108 Sampler.}
\item{Dynamic low-noise RF source}
\item{Driving RF electrodes in ion traps}
\item{Driving acousto-optic modulators}
\item{Form a laser intensity servo with 5108 Sampler}
\end{itemize}
\section{General Description}
The 4410/4412 DDS Urukul card is a 4hp EEM module part of the ARTIQ Sinara family.
It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 4410/4412 DDS Urukul card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 channels of DDS at 1GS/s.
Output frequency from \textless 1 to \textgreater 400 MHz are supported.
The nominal maximum output power of each channel is 10dBm.
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
4410 DDS Urukul comes with AD9910 chips, while 4412 DDS Urukul comes with AD9912 chips instead.
It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output frequencies from \textless 1 to \textgreater 400 MHz are supported. The nominal maximum output power of each channel is 10dBm. Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches (1ns temporal resolution) on each channel provide 70 dB isolation.
4410 DDS Urukul features AD9910 chips, while 4412 DDS Urukul features AD9912 chips. AD9912 is capable of higher frequency precision (~8 \textmu Hz) than the AD9910 (~0.25 Hz). The ARTIQ SU-Servo configuration is only available for AD9910.
% Switch to next column
\vfill\break
@ -276,22 +271,23 @@ RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
\centering
\includegraphics[height=2.2in]{Urukul_FP.jpg}
\includegraphics[height=2.2in]{photo4410.jpg}
\caption{Urukul Card photo}
\caption{Urukul card and front panel}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{4410/4412 DDS Urukul}{https://github.com/sinara-hw/Urukul/}
\section{Electrical Specifications}
Specifications of parameters are based on the datasheets of the
DDS IC(AD9910\footnote{\label{ad9910}https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf},
AD9912\footnote{\label{ad9912}https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}),
clock buffer IC (Si53312\footnote{\label{clock_buffer}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si53312.pdf}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}),
various information from Sinara wiki\footnote{\label{urukul_wiki}https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}
and corresponding test results\footnote{\label{sinara354}https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}.
Specifications of parameters are based on the datasheets of the DDS IC
(AD9910\footnote{\label{ad9910}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf}},
AD9912\footnote{\label{ad9912}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}}),
clock buffer IC (Si53312\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5331x_datasheet.pdf}}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}), Sinara project information\footnote{\label{urukul_wiki}\url{https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}}
and corresponding test results\footnote{\label{sinara354}\url{https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}}.
\begin{table}[h]
\centering
\begin{threeparttable}
@ -332,11 +328,9 @@ and corresponding test results\footnote{\label{sinara354}https://github.com/sina
Resolution & & & & & \\
\hspace{3mm} Frequency\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{urukul_wiki} & & 0.25 & & Hz & AD9910 \\
& & 8 & & $\mu$Hz & AD9912 \\
\hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 16 & & bits & AD9910 \\
& & 14 & & bits & AD9912 \\
\hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 16/14 & & bits & AD9910/AD9912 respectively \\
\hspace{3mm} Digital amplitude\repeatfootnote{ad9910} & & 14 & & bits & AD9910 \\
\hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 8 & & bits & AD9910 \\
& & 10 & & bits & AD9912 \\
\hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 8/10 & & bits & AD9910/AD9912 respectively \\
\hspace{3mm} Temporal (I/O Update)\repeatfootnote{urukul_wiki} & & 4 & & ns & \\
\hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & & 0.5 & & dB & \\
\thickhline
@ -344,14 +338,12 @@ and corresponding test results\footnote{\label{sinara354}https://github.com/sina
\end{threeparttable}
\end{table}
\newpage
The tabulated performance characteristics are produced using the following setup unless otherwise noted.
The tabulated performance characteristics are produced using the following setup unless otherwise noted:
\begin{itemize}
\item 100 MHz input clock into SMA, 10 dBm.
\item Input clock divided by 4.
\item PLL with x40 multiplier.
\item Output frequency at 80 MHz or 81 MHz.
\item 100 MHz input clock into SMA, 10 dBm
\item Input clock divided by 4
\item PLL with x40 multiplier
\item Output frequency at 80 MHz or 81 MHz
\end{itemize}
\begin{table}[h]
@ -399,7 +391,7 @@ The tabulated performance characteristics are produced using the following setup
\newpage
Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\footnote{\label{urukul29}https://github.com/sinara-hw/Urukul/issues/29}. An external 125 MHz clock signal were supplied.
Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\footnote{\label{urukul29}\url{https://github.com/sinara-hw/Urukul/issues/29}}. An external 125 MHz clock signal was supplied.
\newcommand{\ts}{\textsuperscript}
\newcolumntype{Y}{>{\centering\arraybackslash}X}
@ -552,9 +544,7 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
\newpage
The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factor is measured.
The DDS channel is directly connected to an oscilloscope with a 50\textOmega~termination.
The reported values are obtained from the oscilloscope.
The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factors is measured below. The DDS channel is directly connected to an oscilloscope with a 50\textOmega~termination. The reported values are obtained from the oscilloscope.
\begin{multicols}{2}
\begin{figure}[H]
@ -703,7 +693,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=blue,
mark=square,
samples=11,
y filter/.code={\pgfmathparse{\pgfmathresult/0.089807*0.1}\pgfmathresult}
y filter/.expression={y/0.089807 * 0.1}
] coordinates {
(0.0, 0) (0.1, 0.089807) (0.2, 0.179723) (0.3, 0.268852) (0.4, 0.354310) (0.5, 0.441055)
(0.6, 0.526386) (0.7, 0.61233) (0.8, 0.69044) (0.9, 0.75856) (1.0, 0.81703)
@ -713,7 +703,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=orange,
mark=square,
samples=11,
y filter/.code={\pgfmathparse{\pgfmathresult/50.0729*0.1}\pgfmathresult}
y filter/.expression={y/50.0729 * 0.1}
] coordinates {
(0, 0) (0.1, 50.0729) (0.2, 100.309) (0.3, 150.996) (0.4, 200.905) (0.5, 250.004)
(0.6, 297.000) (0.7, 345.980) (0.8, 394.391) (0.9, 442.869) (1.0, 490.651)
@ -723,7 +713,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=green,
mark=square,
samples=11,
y filter/.code={\pgfmathparse{\pgfmathresult/28.4696*0.1}\pgfmathresult}
y filter/.expression={y/28.4696 * 0.1}
] coordinates {
(0, 0) (0.1, 28.4696) (0.2, 57.143) (0.3, 85.776) (0.4, 114.694) (0.5, 143.302)
(0.6, 171.911) (0.7, 200.098) (0.8, 227.816) (0.9, 256.321) (1.0, 281.930)
@ -733,7 +723,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
color=red,
mark=square,
samples=11,
y filter/.code={\pgfmathparse{\pgfmathresult/16.6691*0.1}\pgfmathresult}
y filter/.expression={y/16.6691 * 0.1}
] coordinates {
(0, 0) (0.1, 16.6691) (0.2, 33.3762) (0.3, 49.8844) (0.4, 67.055) (0.5, 83.652)
(0.6, 99.970) (0.7, 116.906) (0.8, 133.368) (0.9, 150.839) (1.0, 167.033)
@ -786,7 +776,7 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
\end{multicols}
\footnotetext{\label{urukul64}https://github.com/sinara-hw/Urukul/issues/64}
\footnotetext{\label{urukul64}\url{https://github.com/sinara-hw/Urukul/issues/64}}
\begin{figure}[H]
\centering
@ -807,61 +797,8 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
\end{figure}
\newpage
\section{Front Panel Drawings}
\begin{multicols}{2}
\begin{center}
\centering
\includegraphics[height=3in]{dds_drawings.pdf}
\captionof{figure}{4410 DDS Urukul front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90498177 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{dds_assembly.pdf}
\captionof{figure}{4410 DDS Urukul front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90498177 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
8 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
9 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\newpage
\section{Urukul Mode Configurations}
Mode of operation is specified by a DIP switch.
The DIP switch can be found at the top right corner of the card.
The following table summarizes the required setting for each mode.
\section{Configuring Operation Mode}
Mode of operation is specified by a DIP switch. The DIP switch can be found at the top right corner of the card. The following table summarizes the required setting for each mode.
\ding{51} indicates ON, while \ding{53} indicates OFF.
\begin{multicols}{2}
@ -887,47 +824,37 @@ The following table summarizes the required setting for each mode.
\end{multicols}
\section{Urukul 1-EEM/2-EEM Modes}
4410/4412 DDS Urukul can operate with either 1 or 2 EEM connections.
It is in 1-EEM mode when only EEM0 is connected, 2-EEM mode when both EEM0 \& EEM1 are connected.
2-EEM mode provides these additional features in comparison to 1-EEM mode.
\begin{itemize}
\item 1 ns temporal resolution RF switches \\
Without EEM1, the only way to access the switches is through the CPLD using SPI. \\
With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver.
1 ns temporal resolution is achieved using the ARTIQ RTIO system.
\section{Urukul Single-/Double-EEM Modes}
\item SU-Servo (4410 DDS Urukul feature) \\
SU-Servo requires both EEM0 \& EEM1 to control multiple DDS channels simultaneously using the QSPI interface.
4410/4412 DDS Urukul cards can operate with either a single or double EEM connections. When only EEM0 is connected, the card will act in single-EEM mode; when both EEM0 and EEM1 are connected, the card will act in double-EEM mode. 2-EEM mode when both EEM0 \& EEM1 are connected. Double-EEM mode provides these additional features in comparison to single-EEM mode:
\begin{itemize}
\item \textbf{1 ns temporal resolution RF switches} \\
Without EEM1, the only way to access the switches is through the CPLD, using SPI. \\
With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system.
\item \textbf{SU-Servo (4410 DDS Urukul feature)} \\
SU-Servo requires both EEM0 \& EEM1 to allow the control of multiple DDS channels simultaneously using the QSPI interface.
\end{itemize}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 4410/4412 DDS Urukul card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\codesection{4410/4412 DDS Urukul}
\subsection{10 MHz Sinusoidal Wave}
Generate a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB.
Both the CPLD and the DDS channels should be initialized.
By default, AD9910 single-tone profiles are programmed to profile 7.
\subsection{10 MHz sinusoidal wave}
Generates a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB. Both the CPLD and the DDS channels should be initialized. By default, AD9910 single-tone profiles are programmed to profile 7.
\inputcolorboxminted{firstline=11,lastline=18}{examples/dds.py}
If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
If the synchronization feature of AD9910 is enabled, RF signal across different channels of the same Urukul can be synchronized. For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
\inputcolorboxminted{firstline=28,lastline=43}{examples/dds.py}
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
It can be negated by adjusting the \texttt{phase} parameter.
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant. It can be negated by adjusting the \texttt{phase} parameter.
\newpage
\subsection{Periodic RF pulse (AD9910 Only)}
This examples demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of AD9910.
By default, RAM profiles are programmed to profile 0.
This example demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of the AD9910. By default, RAM profiles are programmed to profile 0.
\inputcolorboxminted{firstline=53,lastline=91}{examples/dds.py}
@ -939,8 +866,7 @@ The generated RF output of the above example consists of the following features
\item No signal for 3 microseconds.
\item Go back to item 1.
\end{enumerate}
The expected waveform is plotted on the following figure.
Note that phase of the RF pulses may drift gradually.
The expected waveform is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\begin{tikzpicture}[
@ -948,7 +874,7 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
func(\x)= (\x<0) * (0) +
and(\x>=0, \x<2) * (0.42*cos(deg(10*pi*\x))) +
and(\x>=2, \x<3) * (0) +
and(\x>=3, \x<4) * (0.42*cos(deg(10*pi*\x)))) +
and(\x>=3, \x<4) * (0.42*cos(deg(10*pi*\x))) +
and(\x>=4, \x<7) * (0) +
and(\x>=7, \x<7.5) * (0.42*cos(deg(10*pi*\x)));
}
@ -973,15 +899,12 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\end{axis}
\end{tikzpicture}
\subsection{Simple Amplitude Ramp (AD9910 Only)}
\subsection{Simple amplitude ramp (AD9910 only)}
An amplitude ramp of an RF signal can be generated by modifying the \texttt{self.amp} array in the previous example.
\inputcolorboxminted{firstline=95,lastline=98}{examples/dds.py}
The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond.
Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond.
The expected waveform over 1 cycle is plotted on the following figure.
Note that phase of the RF pulses may drift gradually.
The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond. Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond. The expected waveform over 1 cycle is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\begin{tikzpicture}[
@ -1023,26 +946,23 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
\newpage
\subsection{RAM Synchronization (AD9910 Only)}
Multiple RAM channels can also be synchronized.
Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
For example, set phase to 0 for the channels (\texttt{phase=0.0}).
\subsection{RAM synchronization (AD9910 only)}
Multiple RAM channels can also be synchronized. Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}. For example, set phase to 0 for the channels (\texttt{phase=0.0}):
\inputcolorboxminted{firstline=116,lastline=116}{examples/dds.py}
Then, replace the \texttt{run()} function with the following.
Then, replace the \texttt{run()} function with the following:
\inputcolorboxminted{firstline=122,lastline=134}{examples/dds.py}
Two phase-coherent RF signal with the same waveform as the previous figure (from either RAM examples) should be generated.
\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
The SU-Servo feature can be enabled by integrating the 4410 DDS Urukul with a 5108 Sampler.
Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function.
\subsection{Voltage-controlled DDS amplitude (SU-Servo only)}
The SU-Servo feature can be enabled by integrating the 4410 DDS Urukul with a 5108 Sampler. Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function:
\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
First, initialize the RTIO, SU-Servo and its channel.
Note that the programmable gain of the Sampler is $10^0=1$, the input range is [-10V, 10V].
In the following example, the amplitude of DDS is proportional to the ADC input from Sampler. First, initialize the RTIO, SU-Servo and its channel. Note that the programmable gain of the Sampler is $10^0=1$ and the input range is [-10V, 10V].
\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
@ -1055,17 +975,13 @@ When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
Therefore, 3V is converted to 0.3.
Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
SU-Servo encodes the ADC voltage in a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels are capped at 1.0 and the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
The RMS voltage of the DDS channel against the ADC voltage is plotted.
The DDS channel is terminated with 50\textOmega.
A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
\begin{center}
\begin{tikzpicture}[
@ -1098,20 +1014,10 @@ The DDS channel is terminated with 50\textOmega.
\end{tikzpicture}
\end{center}
DDS signal should be attenuated.
High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power.
15 dB attenuation at the digital attenuator was applied in this example.
DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 4410 DDS Urukul in the ARTIQ Sinara crate configuration tool.
The default chip is AD9910 (4410 DDS Urukul), which supports more features.
If you need the higher frequency resolution of the AD9912 (4412 DDS Urukul), leave us a note when placing the order.
To enable SU-Servo feature between 4410 Urukul and 5108 Sampler, specify that SU-Servo is to be integrated into the gateware when placing the order.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{4410/4412 DDS Urukul}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

92
4456.tex
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@ -1,4 +1,4 @@
\include{preamble.tex}
\input{preamble.tex}
\graphicspath{{images/4456}{images}}
\title{4456 Synthesizer Mirny}
@ -13,31 +13,28 @@
\section{Features}
\begin{itemize}
\item{4-channel VCO/PLL.}
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz.}
\item{Up to 13.6 GHz with Almazny mezzanine.}
\item{Higher frequency resolution than Urukul.}
\item{Lower jitter and phase noise.}
\item{Large frequency changes take several milliseconds.}
\item{4-channel VCO/PLL}
\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
\item{Up to 13.6 GHz with Almazny mezzanine}
\item{Higher frequency resolution than Urukul}
\item{Lower jitter and phase noise}
\item{Large frequency changes take several milliseconds}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Low-noise microwave source.}
\item{Quantum state control.}
\item{Driving acousto/electro-optic modulators.}
\item{Low-noise microwave source}
\item{Quantum state control}
\item{Driving acousto/electro-optic modulators}
\end{itemize}
\section{General Description}
The 4456 Synthesizer Mirny card is a 4hp EEM module part of the ARTIQ Sinara family.
It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 channels of PLL frequency synthesis.
Output frequency from 53 MHz to \textgreater 4 GHz are supported.
The range can be expanded up to 13.6 GHz with Almazny mezzanine.
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator.
RF switches on each channel provides at least 50 dB isolation.
It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
% Switch to next column
@ -278,22 +275,24 @@ RF switches on each channel provides at least 50 dB isolation.
\begin{figure}[hbt!]
\centering
\includegraphics[height=2in]{Mirny_FP.pdf}
\includegraphics[height=2in]{photo4456.jpg}
\caption{Mirny Card photo}
\includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
\caption{Mirny card and front panel}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
\section{Electrical Specifications}
Specifications of parameters are based on the datasheets of the
PLL IC(ADF5356\footnote{\label{adf5356}https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}),
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}),
digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}).
Test results are from the Krzysztof Belewicz's thesis ``Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}.
Specifications of parameters are based on the datasheets of the PLL IC
(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
\begin{table}[h]
\centering
@ -342,16 +341,12 @@ Test results are from the Krzysztof Belewicz's thesis ``Microwave synthesizer fo
\newpage
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}.
The SPI signal is driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card.
Mirny is then connected to the RSA5100A spectrum analyzer for measurement.
Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny.
Note that the common-mode choke is not present on the Mirny card.
The following is a comparison between 2 setups at 1 GHz output:
Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
\begin{itemize}
\item Red: Before any modifications
\item Blue: Adding a CM choke with an 100 \textmu F capacitor after the CM choke
\item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
\end{itemize}
\begin{figure}[H]
@ -360,7 +355,7 @@ The following is a comparison between 2 setups at 1 GHz output:
\caption{Phase noise measurement at 1 GHz}
\end{figure}
Phase noise at different output frequencies are then measured.
Phase noise at different output frequencies is then measured:
\newcolumntype{Y}{>{\centering\arraybackslash}X}
@ -396,22 +391,15 @@ Phase noise at different output frequencies are then measured.
\caption{Phase noise measurement}
\end{figure}
\newpage
\codesection{4456 Synthesizer Mirny}
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 4456 Synthesizer Mirny card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{1 GHz Sinusoidal Wave}
Generate a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB.
Both the CPLD and the PLL channels should be initialized.
\subsection{1 GHz sinusoidal wave}
Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
\subsection{ADF5356 Power Control}
Output power can be controlled be configuring the PLL channels individually, in addition to the digital attenuators.
After initialization of the PLL channel (ADF5356), the following line of code can change the output power level.
\subsection{ADF5356 power control}
Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
@ -429,25 +417,17 @@ The parameter corresponds to a specific change of output power according to the
\end{tabular}
\end{center}
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the folowing line.
ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
\newpage
\subsection{Periodic 100\textmu s pulses}
The output can be toggled on and off periodically using the RF switches.
The following code emits a 100\textmu s pulse in every millisecond.
A microwave signal should be programmed in prior (such as the 1 GHz wave example).
The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 4456 Synthesizer Mirny in the ARTIQ Sinara crate configuration tool.
The cards may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{4456 Synthesizer Mirny}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

132
5432.tex
View File

@ -1,4 +1,4 @@
\include{preamble.tex}
\input{preamble.tex}
\graphicspath{{images/5432}{images}}
\title{5432 DAC Zotino}
@ -13,30 +13,26 @@
\section{Features}
\begin{itemize}
\item{32-channel DAC.}
\item{16-bits resolution.}
\item{1 MSPS shared between all channels.}
\item{Output voltage $\pm$10V.}
\item{HD68 connector.}
\item{Can be broken out to BNC/SMA/MCX.}
\item{32-channel DAC}
\item{16-bits resolution}
\item{1 MSPS shared between all channels}
\item{Output voltage $\pm$10V}
\item{HD68 connector}
\item{Can be broken out to BNC/SMA/MCX}
\end{itemize}
\section{Applications}
\begin{itemize}
\item{Controlling setpoints of PID controllers for laser power stabilization.}
\item{Low-frequency arbitrary waveform generation.}
\item{Driving DC electrodes in ion traps.}
\item{Controlling setpoints of PID controllers for laser power stabilization}
\item{Low-frequency arbitrary waveform generation}
\item{Driving DC electrodes in ion traps}
\end{itemize}
\section{General Description}
The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
Each channel supports output voltage from -10 V to 10 V.
All channels can be updated simultaneously.
Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
% Switch to next column
\vfill\break
@ -115,24 +111,33 @@ Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528
\caption{Simplified Block Diagram}
\end{figure}
\begin{figure}[h]
\begin{figure}[hbt!]
\centering
\includegraphics[height=2in]{Zotino_FP.jpg}
\includegraphics[height=2in]{photo5432.jpg}
\caption{Zotino Card photo}
\caption{Zotino card photograph}
\end{figure}
\begin{figure}[hbt!]
\centering
\includegraphics[height=2.3in, angle=90]{Zotino_FP.jpg}
\caption{Zotino front panel}
\end{figure}
% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn
\sourcesection{5432 DAC Zotino}{https://github.com/sinara-hw/Zotino/}
\section{Electrical Specifications}
% \hypersetup{hidelinks}
% \urlstyle{same}
The specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}),
and various information from Sinara wiki\footnote{\label{zotino_wiki}https://github.com/sinara-hw/Zotino/wiki}.
These specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.
\begin{table}[h]
\centering
@ -157,9 +162,7 @@ and various information from Sinara wiki\footnote{\label{zotino_wiki}https://git
\end{threeparttable}
\end{table}
The following are cross-talk and transient behavior of Zotino\footnote{\label{zotino21}https://github.com/sinara-hw/Zotino/issues/21}.
In terms of output noise, it was measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}https://github.com/sinara-hw/Zotino/issues/27}.
The DAC output during noise measurement is 3.5 V.
The following table records the cross-talk and transient behavior of Zotino\footnote{\label{zotino21}\url{https://github.com/sinara-hw/Zotino/issues/21}}. In terms of output noise, measurements were made after a 15-cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}\url{https://github.com/sinara-hw/Zotino/issues/27}}. DAC output during noise measurement was 3.5 V.
\begin{table}[h]
\centering
@ -194,7 +197,7 @@ The DAC output during noise measurement is 3.5 V.
\newpage
Step response are found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observe the waveform\repeatfootnote{zotino21}.
Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observing the waveform\repeatfootnote{zotino21}.
\begin{figure}[hbt!]
\centering
@ -207,12 +210,12 @@ Step response are found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (
\caption{Step response}%
\end{figure}
Far-end crosstalk is measured using the following setup\repeatfootnote{zotino21}.
Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21}:
\begin{enumerate}
\item CH1 as aggressor, CH0 as victim
\item CH0, 2-7 terminated, CH 8-31 open
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables \& connectors.
\item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables and connectors.
\end{enumerate}
\begin{figure}[hbt!]
@ -223,83 +226,24 @@ Far-end crosstalk is measured using the following setup\repeatfootnote{zotino21}
\newpage
\section{Front Panel Drawings}
\begin{multicols}{2}
\codesection{5432 DAC Zotino}
\begin{center}
\centering
\includegraphics[height=3in]{zotino_drawings.pdf}
\captionof{figure}{5432 DAC Zotino front panel drawings}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Standalone)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FRONT PANEL 3U 4HP PIU TYPE2 \\ \hline
2 & 3020716 & 0.02 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
3 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
\end{tabular}
\end{center}
\columnbreak
\begin{center}
\centering
\includegraphics[height=3in]{zotino_assembly.pdf}
\captionof{figure}{5432 DAC Zotino front panel assembly}
\end{center}
\begin{center}
\captionof{table}{Bill of Material (Assembled)}
\tiny
\begin{tabular}{|c|c|c|c|}
\hline
Index & Part No. & Qty & Description \\ \hline
1 & 90503572 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
2 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
3 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
4 & 3010124 & 0.1 & EMC GASKET FABRIC 3U (10PCS) \\ \hline
5 & 3033098 & 0.02 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
6 & 3040012 & 1 & HANDLE 4HP GREY PLASTIC \\ \hline
7 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
8 & 3207075 & 0.01 & SCR M2.5*12 PAN 100 21101-221 \\ \hline
9 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
\end{tabular}
\end{center}
\end{multicols}
\newpage
\section{Example ARTIQ code}
The sections below demonstrate simple usage scenarios of the 5432 DAC Zotino card with the ARTIQ control system.
They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
\subsection{Set output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
\subsection{Setting output voltage}
The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
\newpage
\subsection{Triangular Wave}
A triangular waveform at 10 Hz, 16 V peak-to-peak.
Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
\subsection{Triangular wave}
Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 5432 DAC Zotino in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
\ordersection{5432 DAC Zotino}
\section*{}
\vspace*{\fill}
\input{footnote.tex}
\finalfootnote
\end{document}

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13
preamble.tex
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@ -37,11 +37,24 @@
#1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}.
}
\newcommand*{\sourcesectiond}[4]{
\section{Source}
#1 and #2, like all the Sinara hardware family, are open-source hardware, and design files (schematics, PCB layouts,
BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
}
\newcommand*{\ordersection}[1]{
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
}
\newcommand{\codesection}[1] {
\section{Example ARTIQ Code}
The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system.
The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
}
\newcommand*{\finalfootnote}{
\section*{}
\vspace*{\fill}