5432/5632: fixes

5432/5632: add HVAmp note
5632: init
2025-04-21 20:29:02 +02:00 · 2025-04-21 20:29:02 +02:00 · 2025-04-21 20:29:02 +02:00 · 2025-04-21 20:29:02 +02:00 · 2025-04-21 20:29:02 +02:00 · 2025-04-21 20:29:02 +02:00
60 changed files with 1842 additions and 673 deletions
--- a/.gitignore
+++ b/.gitignore
@ -7,3 +7,4 @@ build
 result

 images/unsorted
+examples/unsorted
--- a/1008.tex
+++ b/1008.tex
@ -0,0 +1,76 @@
+\input{preamble.tex}
+\graphicspath{{images/1008}{images}}
+
+\title{1008 VHDCI Carrier}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{8 channels}
+        \item{8 internal EEM connectors}
+        \item{2 external VHDCI connectors}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Break out VHDCI to extension boards}
+        \item{Carry signals over VHDCI between crates}
+        \item{Low-cost alternative to DRTIO}
+        \item{Adapter for certain KC705 ARTIQ systems}
+    \end{itemize}
+
+\section{General Description}
+
+    The 1008 VHDCI Carrier is a 4hp EEM module, part of the ARTIQ/Sinara family. It is a passive adapter card which converts VHDCI connections to or from EEM connections.
+
+    The 1008 VHDCI Carrier is bidirectional; it can be driven by a core device carrier board, or can drive other cards.
+
+    A pair of VHDCI Carrier cards can be paired with VHDCI SCSI-3 cables to carry EEM signals over short distances between crates. Depending on the application, this can serve as a simple, low-cost, low-latency alternative to multiple core devices and ARTIQ DRTIO.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.5in]{photo1008.jpg}
+    \caption{VHDCI Carrier card}
+    \includegraphics[height=2.5in, angle=90]{fp1008.pdf}
+    \caption{VHDCI Carrier front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{1008 VHDCI Carrier}{https://github.com/sinara-hw/VHDCI_Carrier}
+
+\section{Power}
+
+    Power supply is required when driving EEM cards. 12V should be supplied through barrel jacks (2.50 mm ID, 5.50 mm OD) either in front panel or at back of card.
+
+\ordersection{1008 VHDCI Carrier}
+
+\finalfootnote
+
+\end{document}
--- a/1124.tex
+++ b/1124.tex
@ -4,8 +4,8 @@

 \title{1124 Carrier Kasli 2.0}
 \author{M-Labs Limited}
-\date{October 2024}
-\revision{Revision 2}
+\date{April 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -160,7 +160,7 @@

 \begin{figure}[hbt!]
    \centering
-    \includegraphics[angle=90,height=0.9in]{Kasli_FP.pdf}
+    \includegraphics[angle=90,height=0.9in]{fp1124.jpg}
    \caption{Kasli 2.0 front panel}
 \end{figure}

--- a/1125.tex
+++ b/1125.tex
@ -4,8 +4,8 @@

 \title{1125 Carrier Kasli-SoC}
 \author{M-Labs Limited}
-\date{December 2024}
-\revision{Revision 1} % potentially publishable pending whether block diagram is necessary
+\date{April 2025}
+\revision{Revision 2}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -47,7 +47,11 @@
    \centering
    \includegraphics[height=3in]{photo1125.jpg}
    \caption{Kasli-SoC card}
-    \includegraphics[angle=90,height=1in]{Kasli-SoC_FP.pdf}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[angle=90,height=1in]{fp1125.jpg}
    \caption{Kasli-SoC front panel}
 \end{figure}

@ -107,7 +111,7 @@

    \begin{figure}[hbt!]
        \centering
-        \includegraphics[height=3in]{kasli-soc_dip_switches.jpg}
+        \includegraphics[height=3in]{kasli_soc_dip_switches.jpg}
        \caption{Position of DIP switches, SD card, and reset pins}
    \end{figure}

--- a/1550.tex
+++ b/1550.tex
@ -0,0 +1,250 @@
+\input{preamble.tex}
+\graphicspath{{images}, {images/1550}}
+
+\title{1550 Laser Diode Driver Kirdy}
+\author{M-Labs Limited}
+\date{April 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{307.2 mA max output current, 20-bit resolution}
+        \item{Low noise current source, 300 pA/rtHz @ 1 kHz}
+        \item{Modulation input with DC-18 MHz bandwidth}
+        \item{Monitor photodiode and LD protection}
+        \item{Temperature controller with sub-mK stability}
+        \item{Full digital control over Ethernet}
+        \item{Bias-tee for RF modulation input}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Spectroscopy}
+        \item{Laser cooling}
+        \item{Atomic clocks}
+        \item{Suitable for use with adapter and preinstalled laser assembly or with external laser heads}
+    \end{itemize}
+
+\section{General Description}
+
+    The 1550 Laser Diode Driver Kirdy is an 8hp EEM module, part of the Sinara open hardware family. It serves as a precision laser diode driver, featuring a low-noise current source, low- and high-frequency modulation inputs, and full digital control over Ethernet. Soft start, laser power monitoring with a user-defined trip point, overtemperature protection, and a protection relay minimize the risk of damage to the laser diode.
+
+    1550 Kirdy supports both low-frequency modulation, suitable for laser locks and linewidth reduction, as well as RF modulation injected directly into the diode, typically to add sidebands to the optical output and implement stabilization schemes such as Pound-Drever-Hall and modulation transfer spectroscopy.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+%
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.5in]{photo1550.jpg}
+    \caption{Kirdy card photo}
+    \includegraphics[height=3in, angle=90]{fp1550.pdf}
+    \caption{Kirdy front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{1550 Laser Diode Driver Kirdy}{https://git.m-labs.hk/sinara-hw/kirdy} The associated adapter can be found at the repository \url{https://git.m-labs.hk/sinara-hw/kirdyAdapter/src/branch/master}.
+
+\section{Electrical Specifications}
+
+    These specifications are based upon various information from the Sinara hardware repository\footnote{\label{repo}\url{https://git.m-labs.hk/sinara-hw/kirdy/}}.
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Recommended Operating Conditions}
+        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Input power & & & & & \\
+            \hspace{3mm} Voltage & & 12 & & V \\
+            \hspace{3mm} Current & & & 2.0 & A & \\
+            \hline
+            LF modulation input\textdagger & & & & & \\
+            \hspace{3mm} Voltage & -1 & & 1 & V \\
+            \hspace{3mm} Bandwidth (-3 dB) & & 18 & & MHz & \\
+            \hspace{3mm} Impedance & & 50 / 43.3k & & $\Omega$ & Termination switch on/off \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    1550 Kirdy supports Power-over-Ethernet, PoE+ (802.3at) and PoE (802.3af) standards. Alternatively, power can be provided via input in front panel. When using PoE, TEC output current should be limited to ±2A.
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Electrical Specifications}
+        \begin{tabularx}{\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Photodiode\textdagger & & & & & \\
+            \hspace{3mm} Photocurrent range & 0 & & 3.0 & mA & \\
+            \hspace{3mm} Photocurrent resolution & & 0.8 & & μA & \\
+            \hspace{3mm} Bandwidth (-3 dB) & & 500 & & Hz & \\
+            \hline
+            Laser diode current driver & & & & & \\
+            \hspace{3mm} Resolution & & 0.292 & & μA & \\
+            \hspace{3mm} Control range & & & 307.2 & mA & \\
+            \hspace{3mm} Current limit & & 319 & & mA & \\
+            \hspace{3mm} Compliance & 4.928 & & & V & \\
+            \hspace{3mm} Current noise @ 1 kHz & & & 300 & pA/rtHz & 300 mA DC bias, 10 $\Omega$ load \\
+            \hspace{3mm} RMS noise @ 10 Hz-1 MHz & & & 300 & nA & 300 mA DC bias, 10 $\Omega$ load \\
+            \hspace{3mm} Temp. coefficient & -1 & & +1 & ppm/°C & 50 mA DC bias, tested 43-56 °C \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    \textdagger Circuit may be damaged if photodiode input current exceeds 3.0 mA. It is possible to modify the circuit and reprogram the photodiode current monitor range in the Kirdy driver.
+
+\newpage
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Electrical Specifications, cont.}
+        \begin{tabularx}{\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \thickhline
+            PID temperature controller & & & & & \\
+            \hspace{3mm} Stability & & 1 & & mK & with Kirdy adapter, copper plate; \mbox{subject} to operating conditions \\
+            \hline
+            TEC output & & & & & \\
+            \hspace{3mm} Resolution & & 22.9 & & μA & \\
+            \hspace{3mm} Control range & -3.0 & & 3.0 & A & 12 V power, active cooling \\
+                & -2.0 & & 2.0 & A & with PoE (802.3af) \\
+            \hspace{3mm} Compliance & & 4.3 & & V & \\
+            \hspace{3mm} Voltage reading resolution & & 3.22 & & mV & \\
+            \hspace{3mm} Current reading resolution & & 2.9 & & mA & \\
+            \hline
+            TEC limits & & & & \\
+            \hspace{3mm} Voltage limit range & 0 & & 4.3 & V & \\
+            \hspace{3mm} Voltage limit resolution & & 3.14 & & mV & \\
+            \hspace{3mm} Current limit range & -3.0 & & 3.0 & A & \\
+            \hspace{3mm} Current limit resolution & & 1.57 & & mA & \\
+            \hline
+            NTC thermistor sensor & & & & \\
+            \hspace{3mm} Resolution & & 0.01 & & mK & 10 k$\Omega$, B-constant 3950K, $T_{0}$ 25°C \\
+            \hspace{3mm} Sampling rate & & 16.67 & $>$1000 & Hz & Subject to operating conditions \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+\section{Modulation inputs}
+
+    1550 Kirdy supports two additional modulation inputs via SMA in the front panel, respectively \texttt{HF MOD} for high-frequency and \texttt{LF MOD} for low-frequency. LF modulation input can accept DC input to impose a DC offset on the output current. HF modulation input is AC-coupled and acts as a bias-tee.
+
+    The relationship of modulation input to output current is governed by the following equation:
+
+    \[I_{L} = max(I_{D} + U_{in} \cdot G_{mod}, 0)\]
+
+    where $I_{L}$ is the laser diode current, $I_{D}$ is the laser diode driver output current, $U_{in}$ is the input voltage, and $G_{mod}$ is the modulation gain. Care should be taken that $I_{L}$ always remains under the current limit. Otherwise, overcurrent protection may be triggered.
+
+\newpage
+
+    Modulation gain is adjustable by DIP switch in top right of board. \textit{Exactly one} DIP switch should be enabled at all times. Enabling zero DIP switches may cause serious damage to the laser diode. Other configurations (multiple switches enabled) are invalid, but will not cause damage.
+
+    \begin{multicols}{2}
+
+        \centering
+        \vspace*{10pt}
+        \begin{tabular}{|l|c|}
+            \hline
+            \textbf{Switch} & \textbf{Setting} \\
+            \thickhline
+            1 & 25 mA/V \\
+            2 & 2.5 mA/V \\
+            3 & 0.25 mA/V \\
+            \thickhline
+        \end{tabular}
+        \captionof{table}{DIP switch settings}
+
+    \columnbreak
+
+        \centering
+        \includegraphics[height=1.5in]{kirdy_mod_switch.jpg}
+        \captionof{figure}{Position of DIP switch}
+
+    \end{multicols}
+
+    \begin{multicols}{2}
+
+\section{Configuring termination}
+
+    LF modulation input termination must be configured by setting a physical switch on the board. The termination DIP switch is found at the upper left part of the board, behind the front panel. Turning this switch on adds a 50 $\Omega$ termination to the LF modulation input. Without the switch, the input impedance is approximately 43.4k $\Omega$.
+
+    \vspace*{20pt}
+
+    \columnbreak
+
+        \centering
+        \includegraphics[height=1.5in]{kirdy_imp_switch.jpg}
+        \captionof{figure}{Position of DIP switch}
+
+    \end{multicols}
+
+
+\section{Adapter and Laser Options}
+
+    An optional adapter allows compact lasers in butterfly packages to be mounted directly onto 1550 Kirdy, with a fibre-optic output in the front panel. Multiple single-frequency narrow-linewidth lasers are currently available as preinstalled options for order.
+
+    Alternatively, Kirdy accepts laser signals broken out to the front panel and is suitable for use in driving external laser heads, including commercial or custom ECDLs (with additional piezo driver not included with Kirdy) or injection-locked Fabry-Perot diodes.
+
+\section{Firmware and driver}
+
+    1550 Kirdy features front panel Ethernet and USB-C. Either DFU or OpenOCD can be used to flash firmware; OpenOCD however requires a JTAG adapter.
+
+    Using M-Labs firmware, communication with a host system is performed over Ethernet/TCP in the form of predefined JSON objects. A Python driver implementing these can be found in the Kirdy firmware repo, hosted at \url{https://git.m-labs.hk/M-Labs/kirdy/}, under \texttt{pykirdy}. See inline documentation for descriptions of particular functions and implemented capabilities.
+
+    This driver may be used directly or through the Kirdy GUI, hosted in the same repo. To start the GUI, run the file \texttt{pykirdy/pykirdy/kirdy\_qt.py}, or install it using \texttt{pykirdy/pyproject.toml}. Users familiar with the Nix package manager through ARTIQ or for other reasons may note that the root of the repository includes a \texttt{flake.nix} with an appropriate development shell (e.g. \texttt{nix develop}) including all dependencies.
+
+    Examples in the \texttt{pykirdy} folder further demonstrate the use of the Kirdy driver, as well as the PID autotune temperature regulation feature.
+
+\newpage
+
+    \begin{figure}[hbt!]
+        \centering
+        \includegraphics[width=\textwidth]{kirdy_gui.jpg}
+        \caption{Kirdy driver GUI}
+    \end{figure}
+
+    To first connect to Kirdy, use the "Connect" button in the lower right corner and the IP address and port number assigned to Kirdy. By default, these are \texttt{192.168.1.128} and \texttt{1550} respectively. They can also be changed using commands supplied by the Python driver.
+
+
+\ordersection{1550 Laser Diode Driver Kirdy}
+
+    Kirdy can ship with a single-frequency narrow-linewidth laser pre-mounted and configured. Current wavelength options include 1270-1610 nm and 633-1064 nm. See the M-Labs hardware selection tool or contact M-Labs for prices and details.
+
+\finalfootnote
+
+\end{document}
--- a/2238.tex
+++ b/2238.tex
@ -439,7 +439,7 @@
    \centering
    \includegraphics[height=2in]{photo2238.jpg}
    \caption{MCX-TTL card}
-    \includegraphics[angle=90, height=0.6in]{fp2238.pdf}
+    \includegraphics[angle=90, height=0.5in]{fp2238.jpg}
    \caption{MCX-TTL front panel}
 \end{figure}

--- a/4410-4412.tex
+++ b/4410-4412.tex
@ -3,8 +3,8 @@

 \title{4410/4412 DDS Urukul}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 2}
+\date{January 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -30,11 +30,11 @@
    \end{itemize}

 \section{General Description}
-The 4410/4412 DDS Urukul card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+    The 4410/4412 DDS Urukul card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frequency generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It can also be combined with 5018 ADC Sampler to form the ARTIQ SU-Servo configuration.

    It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output frequencies from \textless 1 to \textgreater 400 MHz are supported. The nominal maximum output power of each channel is 10dBm. Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches (1ns temporal resolution) on each channel provide 70 dB isolation.

-4410 DDS Urukul features AD9910 chips, while 4412 DDS Urukul features AD9912 chips. AD9912 is capable of higher frequency precision (~8 \textmu Hz) than the AD9910 (~0.25 Hz). The ARTIQ SU-Servo configuration is only available for AD9910.
+    4410 DDS Urukul features AD9910 chips, while 4412 DDS Urukul features AD9912 chips. These offer slightly different features and specifications. See below for a comparison between the two.

 % Switch to next column
 \vfill\break
@ -280,15 +280,42 @@ It provides 4 channels of DDS (direct digital synthesis) at 1GS/s. Output freque

 \sourcesection{4410/4412 DDS Urukul}{https://github.com/sinara-hw/Urukul/}

+\section{Model comparison}
+
+    4410 DDS Urukul uses AD9910\repeatfootnote{ad9910} chips, whereas 4412 DDS Urukul uses AD9912\repeatfootnote{ad9912} chips. In general, 4412/AD9912 is capable of much higher frequency resolution, at the cost of more detailed control features provided by 4410/AD9910, such as phase synchronization, digital ramp modulation or DRG, and digital amplitude control. See individual DDS IC datasheets for feature details, especially of AD9910, or ARTIQ code section below for examples of more complex experiments only possible with AD9910. The SUServo configuration is only available for AD9910.
+
+    \begin{table}[h]
+        \centering
+        \begin{threeparttable}
+        \caption{Specification Differences}
+        \begin{tabularx}{0.8\textwidth}{l | c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{AD9910} & \textbf{AD9912} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Resolution & & & & \\
+            \hspace{3mm} Frequency\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{urukul_wiki} & 0.25 & & Hz & \\
+            & & 8 & μHz & \\
+            \hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & 16 & 14 & bits & \\
+            \hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & 8 & 10 & bits & \\
+            \hspace{3mm} Digital amplitude\repeatfootnote{ad9910} & 14 & & bits & \\
+            \hline
+            Power consumption\repeatfootnote{urukul_wiki} & 7 & 6.5 & W & 4x 400 MHz, 10.5 dBm, 52°C \\
+            \hline
+            ARTIQ SUServo available & Yes & No & & \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
 \section{Electrical Specifications}

    Specifications of parameters are based on the datasheets of the DDS IC
    (AD9910\footnote{\label{ad9910}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf}} ,
-AD9912\footnote{\label{ad9912}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}}),
-clock buffer IC (Si53312\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5331x_datasheet.pdf}}),
-digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}), Sinara project information\footnote{\label{urukul_wiki}\url{https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}}
-and corresponding test results\footnote{\label{sinara354}\url{https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}}.
-\begin{table}[h]
+    AD9912AD9912\footnote{\label{ad9912}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9912.pdf}}),
+    clock buffer IC (Si53312\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/SkyWorks/SL/documents/public/data-sheets/Si5331x_datasheet.pdf}}), digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}), Sinara project information\footnote{\label{urukul_wiki}\url{https://github.com/sinara-hw/Urukul/wiki\#details-specification-and-typical-performance-data}} and corresponding test results\footnote{\label{sinara354}\url{https://github.com/sinara-hw/sinara/issues/354\#issuecomment-352859041}}.
+
+    \begin{table}[hbt!]
    \centering
    \begin{threeparttable}
    \caption{Recommended Operating Conditions}
@ -303,13 +330,29 @@ and corresponding test results\footnote{\label{sinara354}\url{https://github.com
        & 12.8 &  &  240 & MHz & AD9910, PLL enabled, 4x clock division \\
        & 11 &  &  200 & MHz & AD9912, PLL enabled, no clock division \\
        & 44 &  &  800 & MHz & AD9912, PLL enabled, 4x clock division \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+\newpage
+
+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Recommended Operating Conditions, cont.}
+        \begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
            \hspace{3mm} Nominal input power\repeatfootnote{clock_buffer} & & 10 & & dBm & \\
            \thickhline
        \end{tabularx}
        \end{threeparttable}
        \end{table}

-\begin{table}[h]
+    \begin{table}[hbt!]
        \centering
        \begin{threeparttable}
        \caption{RF Output Specifications}
@ -326,11 +369,6 @@ and corresponding test results\footnote{\label{sinara354}\url{https://github.com
            Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
            \hline
            Resolution & & & & & \\
-    \hspace{3mm} Frequency\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{urukul_wiki} & & 0.25 & & Hz & AD9910 \\
-     & & 8 & & $\mu$Hz & AD9912 \\
-    \hspace{3mm} Phase offset\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 16/14 & & bits & AD9910/AD9912 respectively \\
-    \hspace{3mm} Digital amplitude\repeatfootnote{ad9910} & & 14 & & bits & AD9910 \\
-    \hspace{3mm} DAC full scale current\repeatfootnote{ad9910}\textsuperscript{,}\repeatfootnote{ad9912} & & 8/10 & & bits & AD9910/AD9912 respectively \\
            \hspace{3mm} Temporal (I/O Update)\repeatfootnote{urukul_wiki} & & 4 & & ns & \\
            \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & & 0.5 & & dB & \\
            \thickhline
@ -338,52 +376,36 @@ and corresponding test results\footnote{\label{sinara354}\url{https://github.com
        \end{threeparttable}
        \end{table}

-The tabulated performance characteristics are produced using the following setup unless otherwise noted:
-\begin{itemize}
-    \item 100 MHz input clock into SMA, 10 dBm
-    \item Input clock divided by 4
-    \item PLL with x40 multiplier
-    \item Output frequency at 80 MHz or 81 MHz
-\end{itemize}
-
-\begin{table}[h]
+    \begin{table}[hbt!]
+        \centering
        \begin{threeparttable}
        \caption{Electrical Characteristics}
-\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+        \begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
            \thickhline
-    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
            \textbf{Unit} & \textbf{Conditions} \\
            \hline
-    Digital attenuator glitch duration\repeatfootnote{sinara354} & $t_s$ & & 100 & & ns & \\
+            Digital attenuator glitch duration\repeatfootnote{sinara354} & & 100 & & ns & \\
            \hline
-    RF switch\repeatfootnote{sinara354} & & & & & &\\
-    \hspace{3mm} Rise to 90\% & $t_{on}$ & & 100 & & ns & \\
-    \hspace{3mm} Isolation & & & 70 & & dB & \\
-    \hspace{3mm} Turn-on chirp & $\gamma$ & & & 0.1 & deg/s & Excluding the first $\mu$s\\
+            RF switch\repeatfootnote{sinara354} & & & & &\\
+            \hspace{3mm} Rise to 90\% & & 100 & & ns & \\
+            \hspace{3mm} Isolation & & 70 & & dB & \\
+            \hspace{3mm} Turn-on chirp & & & 0.1 & deg/s & Excluding the first $\mu$s\\
            \hline
-    Crosstalk\repeatfootnote{sinara354} & & & -84 & & dB & Victim RF switch opened \\
-    & & & -110 & & dB & Victim RF switch closed \\
+            Crosstalk\repeatfootnote{sinara354} & & -84 & & dB & Victim RF switch opened \\
+            & & -110 & & dB & Victim RF switch closed \\
            \hline
-    Cross-channel-intermodulation\repeatfootnote{sinara354} & & & -90 & & dB & \\
+                Cross-channel-intermodulation\repeatfootnote{sinara354} & & -90 & & dB & \\
                \hline
-    Phase noise\repeatfootnote{sinara354} & $\mathcal{L}(f)$ & & -85 & & dBc/Hz & 0.1 Hz \\
-    & & & -95 & & dBc/Hz & 1 Hz \\
-    & & & -107 & & dBc/Hz & 10 Hz \\
-    & & & -116 & & dBc/Hz & 100 Hz \\
-    & & & -126 & & dBc/Hz & 1 kHz \\
-    & & & -133 & & dBc/Hz & 10 kHz \\
-    & & & -135 & & dBc/Hz & 100 kHz \\
-    & & & -128 & & dBc/Hz & 1 MHz \\
-    & & & -149 & & dBc/Hz & 10 MHz \\
-    \hline
-    Second-order harmonics\repeatfootnote{sinara354} & & & -40 & & dB & 6 dBm output \\
-    & & & -34 & & dB & 10.5 dBm output \\
-    \hline
-    Third-order harmonics\repeatfootnote{sinara354} & & & -54 & & dB & 6 dBm output \\
-    & & & -28 & & dB & 10.5 dBm output \\
-    \hline
-    Power consumption (AD9910)\repeatfootnote{urukul_wiki} & $P$ & & 7 & & W & 4x 400 MHz, 10.5 dBm, 52\degree C\\
-    Power consumption (AD9912)\repeatfootnote{urukul_wiki} & $P$ & & 6.5 & & W & 4x 400 MHz, 10.5 dBm, 52\degree C\\
+                Phase noise\repeatfootnote{sinara354} & & -85 & & dBc/Hz & 0.1 Hz \\
+                & & -95 & & dBc/Hz & 1 Hz \\
+                & & -107 & & dBc/Hz & 10 Hz \\
+                & & -116 & & dBc/Hz & 100 Hz \\
+                & & -126 & & dBc/Hz & 1 kHz \\
+                & & -133 & & dBc/Hz & 10 kHz \\
+                & & -135 & & dBc/Hz & 100 kHz \\
+                & & -128 & & dBc/Hz & 1 MHz \\
+                & & -149 & & dBc/Hz & 10 MHz \\
            \thickhline
        \end{tabularx}
        \end{threeparttable}
@ -391,6 +413,34 @@ The tabulated performance characteristics are produced using the following setup

 \newpage

+    \begin{table}[hbt!]
+        \centering
+        \begin{threeparttable}
+        \caption{Electrical Characteristics, cont.}
+        \begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            \hline
+            Second-order harmonics\repeatfootnote{sinara354} & & -40 & & dB & 6 dBm output \\
+            & & -34 & & dB & 10.5 dBm output \\
+            \hline
+            Third-order harmonics\repeatfootnote{sinara354} & & -54 & & dB & 6 dBm output \\
+            & & -28 & & dB & 10.5 dBm output \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    The tabulated performance characteristics above were produced using the following setup unless otherwise noted:
+
+    \begin{itemize}
+        \item 100 MHz input clock into SMA, 10 dBm
+        \item Input clock divided by 4
+        \item PLL with x40 multiplier
+        \item Output frequency at 80 MHz or 81 MHz
+    \end{itemize}
+
 Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\footnote{\label{urukul29}\url{https://github.com/sinara-hw/Urukul/issues/29}}. An external 125 MHz clock signal was supplied.

 \newcommand{\ts}{\textsuperscript}
@ -432,6 +482,8 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
 \end{threeparttable}
 \end{table}

+\newpage
+
 \begin{table}[hbt!]
 \begin{threeparttable}
 \caption{Harmonic content with 10.0 dB digital attenuation}
@ -468,9 +520,7 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
 \end{threeparttable}
 \end{table}

-\newpage
-
-\begin{table}[h]
+\begin{table}[hbt!]
 \begin{threeparttable}
 \caption{Harmonic content with 20.0 dB digital attenuation}
 \begin{tabularx}{\textwidth}{| c | Y | Y | Y | Y | Y | Y | Y | Y | Y |}
@ -506,6 +556,8 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
 \end{threeparttable}
 \end{table}

+\newpage
+
 \begin{table}[hbt!]
 \begin{threeparttable}
 \caption{Harmonic content with 31.5 dB digital attenuation}
@ -542,9 +594,7 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
 \end{threeparttable}
 \end{table}

-\newpage
-
-The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factors is measured below. The DDS channel is directly connected to an oscilloscope with a 50\textOmega~termination. The reported values are obtained from the oscilloscope.
+The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factors is measured below. The DDS channel is directly connected to an oscilloscope with a 50\textOmega$\sim$termination. The reported values are obtained from the oscilloscope.

 \begin{multicols}{2}
 \begin{figure}[H]
@ -663,6 +713,8 @@ The RMS voltage of a 4410 DDS Urukul channel at different amplitude scale factor

 \end{multicols}

+\newpage
+
 The ideal RMS voltage is described by the linear function $V_\mathrm{rms,ideal}(\mathrm{ASF})=\frac{V_\mathrm{rms}(0.1)}{0.1}*\mathrm{ASF}$.
 The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\mathrm{rms,ideal}(1)$) is shown below.

@ -796,8 +848,16 @@ The measured RMS voltage divided by the full scale ideal RMS voltage (i.e. $V_\m
    \caption{Attenuator step from 31 to 32 digital\\(major carry glitch)\repeatfootnote{sinara354}}
 \end{figure}

+\section{Front panel LEDs}
+
+    4410/4412 Urukul features a number of indicator LEDs in the front panel. Each of four channel SMA connectors is accompanied by a green LED, used to indicate that RF output is enabled, and a red LED, which activates to indicate a DDS synchronization/PLL issue. Note that when bypassing PLL in ARTIQ (see below) LED may stay on.
+
+    Two additional LEDs indicate power good (green) and overtemperature (red).
+
 \newpage
+
 \section{Configuring Operation Mode}
+
    Mode of operation is specified by a DIP switch. The DIP switch can be found at the top right corner of the card. The following table summarizes the required setting for each mode.
    \ding{51} indicates ON, while \ding{53} indicates OFF.

@ -826,22 +886,40 @@ Mode of operation is specified by a DIP switch. The DIP switch can be found at t

 \section{Urukul Single-/Double-EEM Modes}

-4410/4412 DDS Urukul cards can operate with either a single or double EEM connections. When only EEM0 is connected, the card will act in single-EEM mode; when both EEM0 and EEM1 are connected, the card will act in double-EEM mode.  2-EEM mode when both EEM0 \& EEM1 are connected. Double-EEM mode provides these additional features in comparison to single-EEM mode:
-\begin{itemize}
-    \item \textbf{1 ns temporal resolution RF switches} \\
-    Without EEM1, the only way to access the switches is through the CPLD, using SPI. \\
-    With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system.
+    4410/4412 DDS Urukul cards can operate with either a single or double EEM connections. When only EEM0 is connected, the card will act in single-EEM mode; when both EEM0 and EEM1 are connected, the card will act in double-EEM mode.

-    \item \textbf{SU-Servo (4410 DDS Urukul feature)} \\
-    SU-Servo requires both EEM0 \& EEM1 to allow the control of multiple DDS channels simultaneously using the QSPI interface.
+    Double-EEM mode additionally provides 1 ns temporal resolution RF switches and multi-chip synchronisation. Without EEM1, the only way to access the switches is through the CPLD, using SPI. With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver. 1 ns temporal resolution can then be achieved using the ARTIQ RTIO system. Double-EEM mode is also recommended for the SUServo configuration.

-\end{itemize}
+\sysdescsection
+
+    4410/4412 Urukul should be entered in the peripherals list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+            "type": "urukul",
+            "dds": "ad9910", // or "ad9912", as appropriate
+            "ports": [0, 1], // second port is optional
+            "synchronization": true, // or false, for AD9910 only
+            "clk_sel": 2, // select 0 to 2 for clock source
+            "pll_en": 0 // PLL bypass, for higher external frequencies
+            "refclk": 125e6, // for external clock signal
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 and 1 with the EEM port numbers used on the core device. Any ports can be used. For single-EEM mode, simply specify only one port. The \texttt{synchronization} field is boolean, false by default, and only applies to AD9910. In the \texttt{clk\_sel} field, \texttt{0} represents the internal 100 MHz oscillator, \texttt{1} represents SMA input, and \texttt{2} represents MMCX input. The \texttt{pll\_en} field may be specified \texttt{0} or \texttt{1} and is \texttt{1} by default.
+
+    Note that the SUServo configuration requires a different system description entry. See SUServo section below.

 \newpage

 \codesection{4410/4412 DDS Urukul}

+    For details of AD9910 capabilities, operation modes, profiles, signals, etc., see also the corresponding datasheet, e.g. \url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf}.
+
    \subsection{10 MHz sinusoidal wave}
+
    Generates a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB. Both the CPLD and the DDS channels should be initialized. By default, AD9910 single-tone profiles are programmed to profile 7.

    \inputcolorboxminted{firstline=11,lastline=18}{examples/dds.py}
@ -853,7 +931,9 @@ If the synchronization feature of AD9910 is enabled, RF signal across different
    Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant. It can be negated by adjusting the \texttt{phase} parameter.

 \newpage
+
    \subsection{Periodic RF pulse (AD9910 Only)}
+
    This example demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of the AD9910. By default, RAM profiles are programmed to profile 0.

    \inputcolorboxminted{firstline=53,lastline=91}{examples/dds.py}
@ -866,8 +946,7 @@ The generated RF output of the above example consists of the following features
        \item No signal for 3 microseconds.
        \item Go back to item 1.
    \end{enumerate}
-The expected waveform is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
-Urukul was operated with a 50$\Omega$ termination to produce the waveform.
+    The expected waveform is plotted on the following figure. Note that phase of the RF pulses may drift gradually. Urukul was operated with 50$\Omega$ termination for this waveform.

    \begin{tikzpicture}[
        declare function={
@ -900,12 +979,12 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
    \end{tikzpicture}

    \subsection{Simple amplitude ramp (AD9910 only)}
+
    An amplitude ramp of an RF signal can be generated by modifying the \texttt{self.amp} array in the previous example.

    \inputcolorboxminted{firstline=95,lastline=98}{examples/dds.py}

-The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond. Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond. The expected waveform over 1 cycle is plotted on the following figure. Note that phase of the RF pulses may drift gradually.
-Urukul was operated with a 50$\Omega$ termination to produce the waveform.
+    The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond. Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond. The expected waveform over 1 cycle is plotted on the following figure. Note that phase of the RF pulses may drift gradually. Urukul was operated with 50$\Omega$ termination for this waveform.

    \begin{tikzpicture}[
        declare function={
@ -939,7 +1018,6 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
        ymin=-0.7, ymax=0.7, ytick={-0.5,...,0,...,0.5}, ylabel=Voltage ($V$),
        xmin=0, xmax=11.5, xtick={0,...,11}, xlabel=Time ($\mu s$),
    ]
-
    \addplot[blue, samples=1500, domain=0:11]{func(x)};
    \end{axis}
    \end{tikzpicture}
@ -947,6 +1025,7 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
 \newpage

    \subsection{RAM synchronization (AD9910 only)}
+
    Multiple RAM channels can also be synchronized. Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}. For example, set phase to 0 for the channels (\texttt{phase=0.0}):

    \inputcolorboxminted{firstline=116,lastline=116}{examples/dds.py}
@ -955,66 +1034,10 @@ Then, replace the \texttt{run()} function with the following:

    \inputcolorboxminted{firstline=122,lastline=134}{examples/dds.py}

-Two phase-coherent RF signal with the same waveform as the previous figure (from either RAM examples) should be generated.
+    Two phase-coherent RF signals with the same waveform as the previous figure (from either RAM examples) should be generated.

-\subsection{Voltage-controlled DDS amplitude (SU-Servo only)}
-The SU-Servo feature can be enabled by integrating the 4410 DDS Urukul with a 5108 Sampler. Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function:
-
-\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
-
-In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.  First, initialize the RTIO, SU-Servo and its channel. Note that the programmable gain of the Sampler is $10^0=1$ and the input range is [-10V, 10V].
-
-\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
-
-Next, setup the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
-
-\inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
-
-Then, configure the DDS frequency to 10 MHz with 3V input offset.
-When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
-
-\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
-
-SU-Servo encodes the ADC voltage in a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels are capped at 1.0 and the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
-
-Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
-
-\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
-
-A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
-
-\begin{center}
-\begin{tikzpicture}[
-    declare function={
-        func(\x)= and(\x>=-10, \x<-7) * (160) +
-            and(\x>=-7, \x<3) * (16*(3-x)) +
-            and(\x>=3, \x<10) * (0);
-    }
-]
-\begin{axis}[
-    axis x line=middle, axis y line=middle,
-    every axis x label/.style={
-        at={(axis description cs:0.5,-0.1)},
-        anchor=north,
-    },
-    every axis y label/.style={
-        at={(ticklabel* cs:1.05)},
-        anchor=south,
-    },
-    minor x tick num=3,
-    grid=both,
-    height=8cm,
-    width=12cm,
-    ymin=-5, ymax=180, ytick={0,16,...,160}, ylabel=DDS RMS Voltage ($mV_{rms}$),
-    xmin=-10, xmax=10, xtick={-10,-8,...,10}, xlabel=Sampler Voltage ($V$),
-]
-
-\addplot[very thick, blue, samples=21, domain=-10:10]{func(x)};
-\end{axis}
-\end{tikzpicture}
-\end{center}
-
-DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
+% Direct input to avoid issues with minted
+\input{shared/suservo.tex}

 \ordersection{4410/4412 DDS Urukul}

--- a/4456-4457.tex
+++ b/4456-4457.tex
@ -1,10 +1,10 @@
 \input{preamble.tex}
-\graphicspath{{images/4456}{images}}
+\graphicspath{{images/4456-4457}{images}}

-\title{4456 Synthesizer Mirny}
+\title{4456 Synthesizer Mirny / 4457 HF Synthesizer Mirny + Almazny}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 1}
+\date{April 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -13,12 +13,11 @@
 \section{Features}

 \begin{itemize}
-\item{4-channel VCO/PLL}
-\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
-\item{Up to 13.6 GHz with Almazny mezzanine}
-\item{Higher frequency resolution than Urukul}
-\item{Lower jitter and phase noise}
-\item{Large frequency changes take several milliseconds}
+    \item{4-channel wide-band PLL/VCO-based microwave frequency synthesiser}
+    \item{Output frequency ranges from 53 MHz to \textgreater 4 GHz for 4456 Mirny only}
+    \item{Up to 12 GHz with 4457 Almazny}
+    \item{Higher frequency resolution than 4410/4412 Urukul}
+    \item{Lower jitter, phase noise than 4410/4412 Urukul}
 \end{itemize}

 \section{Applications}
@ -30,12 +29,11 @@
 \end{itemize}

 \section{General Description}
-The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+    The 4456 Synthesizer Mirny card is a 4hp EEM module; the 4457 HF Synthesizer Mirny + Almazny card, consisting of 4456 Mirny plus the 4-channel Almazny HF mezzanine, is a 8hp EEM module. Both Synthesizer cards add microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.

-It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
-
-Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
+    Both cards provide 4 channels of PLL frequency synthesis. 4456 Synthesizer Mirny supports output frequencies from 53 MHz to \textgreater 4GHz. As 4457 HF Synthesizer with Almazny mezzanine this range is expanded up to 12 GHz.

+    Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provide at least 50 dB isolation.

 % Switch to next column
 \vfill\break
@ -275,16 +273,30 @@ Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF sw

 \begin{figure}[hbt!]
    \centering
-    \includegraphics[height=2in]{photo4456.jpg}
-    \includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
-    \caption{Mirny card and front panel}
+    \includegraphics[height=2in]{photo4457.jpg}
+    \caption{Mirny + Almazny card}
 \end{figure}

 % For wide tables, a single column layout is better. It can be switched
 % page-by-page.
 \onecolumn

-\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
+\begin{figure}[hbt!]
+    \subfloat[\centering Mirny and Almazny front panels]{{
+        \begin{minipage}[b]{0.5\linewidth}
+            \centering
+            \includegraphics[height=3.4in, angle=90]{fp4457.jpg} \\
+            \vspace{0.1in}
+            \includegraphics[height=3.4in, angle=90]{fp4456.jpg}
+            \vspace{0.3in}
+        \end{minipage}
+    }}
+    \subfloat[\centering Mirny, top-down view]{{
+        \includegraphics[height=2.5in]{photo4456.jpg}
+    }}
+\end{figure}
+
+\sourcesectiond{4456 Synthesizer Mirny}{the 4457 Almazny mezzanine}{https://github.com/sinara-hw/mirny}{https://github.com/sinara-hw/Almazny}

 \section{Electrical Specifications}

@ -326,28 +338,40 @@ Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for dr
        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
        \textbf{Unit} & \textbf{Conditions} \\
        \hline
-    Frequency & 53.125 &  & 4000 & MHz & \\
+        Frequency & 53.125 &  & 4000 & MHz & 4456 Mirny only \\
+        & & & 12000 & MHz & With Almazny mezzanine \\
        \hline
        Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
        \hline
-    Resolution & \multicolumn{4}{c|}{} & \\
-    \hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
-    \hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
-    \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
-    \thickhline
    \end{tabularx}
    \end{threeparttable}
    \end{table}

 \newpage

-Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
+\begin{table}[h]
+    \centering
+    \begin{threeparttable}
+    \caption{Output Specifications, cont.}
+    \begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+        \thickhline
+        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+        \textbf{Unit} & \textbf{Conditions} \\
+        \hline
+        Lock time\repeatfootnote{adf5356} & & 1.7 & & ms & \\
+        \hline
+        Resolution & & & & \\
+        \hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{3}{c|}{52} & bits & \\
+        \hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{3}{c|}{24} & bits & \\
+        \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{3}{c|}{0.5} & dB & \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+    Phase noise performance of 4456 Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. 4456 Mirny was then connected to the RSA5100A spectrum analyzer for measurement.

    Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
-\begin{itemize}
-    \item Red: Before any modifications
-    \item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
-\end{itemize}

    \begin{figure}[H]
        \centering
@ -355,6 +379,13 @@ Noise response spike can be improved by inserting an additional common-mode chok
        \caption{Phase noise measurement at 1 GHz}
    \end{figure}

+    \begin{itemize}
+        \item Red: Before any modifications
+        \item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
+    \end{itemize}
+
+\newpage
+
    Phase noise at different output frequencies is then measured:

    \newcolumntype{Y}{>{\centering\arraybackslash}X}
@ -383,21 +414,59 @@ Phase noise at different output frequencies is then measured:
    \end{threeparttable}
    \end{table}

-\newpage
-
    \begin{figure}[H]
        \centering
        \includegraphics[height=3in]{mirny_phase_noise_frequency.png}
        \caption{Phase noise measurement}
    \end{figure}

-\codesection{4456 Synthesizer Mirny}
+\section{Programmable LEDs}
+
+    4456 Mirny features several status LEDs, including a two per output channel. One per channel displays RF switch status.
+
+    The 4457 Almazny mezzanine features an additional row of LEDs, one per output channel, without a fixed purpose. The associated ARTIQ module allows programming these directly through the channel \texttt{set} method.
+
+\newpage
+\sysdescsection
+
+    4456 Synthesizer Mirny must be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "mirny",
+                "ports": 0,
+                "clk_sel": "mmcx", // optional
+                "refclk": 125e6 // optional
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port number used on the core device. Any port can be used. The \texttt{clk\_sel} field is optional and may be specified as one of either \texttt{xo}, \texttt{mmcx}, or \texttt{sma}. The default is \texttt{xo}. The \texttt{refclk} field is optional and the default is \texttt{100e6}.
+
+    For 4457 Mirny + Almazny, one field must be added:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "mirny",
+                "almazny": true,
+                "ports": 0
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+\codesection{4456 Synthesizer Mirny and 4457 Mirny + Almazny}

    \subsection{1 GHz sinusoidal wave}
    Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.

    \inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}

+    \subsection{Almazny paired output}
+
+    Mirny and Almazny output channels are paired, and Almazny output channels output twice the frequency of the main Mirny outputs. To set Almazny HF outputs for 4457 HF Synthesizer, set the Mirny outputs to one-half the desired frequency. The above code, run with 4457 HF Synthesizer, will also output 2GHz from Almazny HF0.
+
    \subsection{ADF5356 power control}
    Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:

@ -426,7 +495,7 @@ The output can be toggled on and off periodically using the RF switches. The fol

    \inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}

-\ordersection{4456 Synthesizer Mirny}
+\ordersection{4456 Synthesizer Mirny or 4457 HF Synthesizer Mirny + Almazny}

 \finalfootnote

--- a/5108.tex
+++ b/5108.tex
@ -3,8 +3,8 @@

 \title{5108 ADC Sampler}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 1}
+\date{January 2025}
+\revision{Revision 2}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -31,7 +31,8 @@
    \end{itemize}

 \section{General Description}
-The 5108 ADC Sampler is a 8hp EEM module, part of the ARTIQ/Sinara family. It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+    The 5108 ADC Sampler is an 8hp EEM module, part of the ARTIQ/Sinara family. It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It can also be combined with 4410 DDS Urukul to form the ARTIQ SU-Servo configuration.

    It provides eight analog-to-digital channels, exposed by eight BNC connectors. Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V. All channels can be sampled simultaneously. Channels can broken out to SMA by adding a 5528 SMA-IDC card.

@ -493,9 +494,11 @@ Bandwidth of small signal and large signal input is shown below\repeatfootnote{s

 \newpage

-\section{Configuring Termination}
    \begin{multicols}{2}
-The input termination must be configured by setting physical switches on the board. The termination switches are found at the middle left part of the card are by-channel. Switching the termination switches on adds a 50\textOmega~termination between the differential input signals.
+
+\section{Configuring Termination}
+
+    The input termination must be configured by setting physical switches on the board. The termination switches are found at the middle left part of the card and by-channel. Setting these switches to \texttt{on} adds a 50\textOmega~termination between the differential input signals.

    Regardless of switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.

@ -508,6 +511,23 @@ Regardless of switch configurations, the differential input signals are separate
    \end{center}
    \end{multicols}

+\sysdescsection
+
+    5108 Sampler should be entered into the peripherals list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "sampler",
+                "ports": [0, 1]
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 and 1 with the EEM port numbers used on the core device. Any ports can be used.
+
+\newpage
+
 \codesection{5108 ADC Sampler}

    \subsection{Get input voltage}
@ -515,67 +535,8 @@ The following example initializes the Sampler card with 1x gain on all ADC chann

    \inputcolorboxminted{firstline=9,lastline=21}{examples/sampler.py}

-\newpage
-
-\subsection{Voltage-controlled DDS amplitude (SU-Servo only)}
-SU-Servo configuration can be enabled by integrating the 5108 ADC Sampler with 4410 DDS Urukul. Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function:
-\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
-In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
-
-First, initialize the RTIO, SU-Servo and its channel with 1x gain.
-
-\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
-
-Next, set up the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
-
-\inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
-
-Then, configure the DDS frequency to 10 MHz with 3V input offset. When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
-
-\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
-
-SU-Servo encodes the ADC voltage in a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels are capped at 1.0; the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
-
-Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
-
-\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
-
-\newpage
-
-A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
-
-\begin{center}
-\begin{tikzpicture}[
-    declare function={
-        func(\x)= and(\x>=-10, \x<-7) * (160) +
-            and(\x>=-7, \x<3) * (16*(3-x)) +
-            and(\x>=3, \x<10) * (0);
-    }
-]
-\begin{axis}[
-    axis x line=middle, axis y line=middle,
-    every axis x label/.style={
-        at={(axis description cs:0.5,-0.1)},
-        anchor=north,
-    },
-    every axis y label/.style={
-        at={(ticklabel* cs:1.05)},
-        anchor=south,
-    },
-    minor x tick num=3,
-    grid=both,
-    height=8cm,
-    width=12cm,
-    ymin=-5, ymax=180, ytick={0,16,...,160}, ylabel=DDS RMS Voltage ($mV_{rms}$),
-    xmin=-10, xmax=10, xtick={-10,-8,...,10}, xlabel=Sampler Voltage ($V$),
-]
-
-\addplot[very thick, blue, samples=21, domain=-10:10]{func(x)};
-\end{axis}
-\end{tikzpicture}
-\end{center}
-
-DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
+% Direct input to avoid issues with minted
+\input{shared/suservo.tex}

 \ordersection{5108 ADC Sampler}

--- a/5432.tex
+++ b/5432.tex
@ -1,10 +1,11 @@
 \input{preamble.tex}
-\graphicspath{{images/5432}{images}}
+\input{shared/dactino.tex}
+\graphicspath{{images/5432}, {images}}

 \title{5432 DAC Zotino}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 2}
+\date{January 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -14,9 +15,9 @@

    \begin{itemize}
        \item{32-channel DAC}
-\item{16-bits resolution}
+        \item{16-bit resolution}
        \item{1 MSPS shared between all channels}
-\item{Output voltage $\pm$10V}
+        \item{Output voltage ±10V}
        \item{HD68 connector}
        \item{Can be broken out to BNC/SMA/MCX}
    \end{itemize}
@ -24,15 +25,12 @@
 \section{Applications}

    \begin{itemize}
-\item{Controlling setpoints of PID controllers for laser power stabilization}
        \item{Low-frequency arbitrary waveform generation}
+        \item{Driving coil amplifiers for magnetic field control}
        \item{Driving DC electrodes in ion traps}
    \end{itemize}

-\section{General Description}
-The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
-
-It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
+\generaldescription{5432 DAC Zotino}{high-speed 5632 DAC Fastino}

 % Switch to next column
 \vfill\break
@ -136,7 +134,7 @@ It provides four groups of eight analog channels each, exposed by one HD68 conne
    % \hypersetup{hidelinks}
    % \urlstyle{same}
    These specifications are based on the datasheet of the DAC IC
-(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
+    (AD5372\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
    and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.

    \begin{table}[h]
@ -147,6 +145,7 @@ and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{ht
        \thickhline
        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
        \textbf{Unit} & \textbf{Conditions} \\
+        Sampling rate & & 1 & & MSPS & shared across channels \\
        \hline
        Output voltage & -10 & & 10 & V & \\
        \hline
@ -224,23 +223,28 @@ Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21
        \caption{Step crosstalk}
    \end{figure}

-\newpage
+\section{LEDs}

-\codesection{5432 DAC Zotino}
-
-\subsection{Setting output voltage}
-The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
-
-\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
+    5432 DAC Zotino provides eight user LEDs in the front panel. These are directly accessible in ARTIQ RTIO.

 \newpage

-\subsection{Triangular wave}
-Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+\sysdescsection

-Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
+    5432 DAC Zotino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:

-\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "zotino",
+                "ports": [0]
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port used on the core device. Any port may be used.
+
+\codesectiondactino{5432 DAC Zotino}{Zotino}{zotino.py}

 \ordersection{5432 DAC Zotino}

--- a/5568.tex
+++ b/5568.tex
@ -3,8 +3,8 @@

 \title{5568 HD68-IDC}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 1}
+\date{April 2025}
+\revision{Revision 2}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -32,7 +32,7 @@
 \end{itemize}

 \section{General Description}
-The 5568 HD68-IDC card is a 4hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
+The 5568 HD68-IDC card is an 8hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.

 Each card supports 32 channels, with one HD68 connector and four IDC connectors. Each IDC connector supports 8 channels. All 32 channels can be accessed using an external HD68 cable.

@ -68,8 +68,8 @@ Each card supports 32 channels, with one HD68 connector and four IDC connectors.

 \begin{figure}[h]
    \centering
-    \includegraphics[height=3.5in, angle=90]{photo5568.jpg}
-    \includegraphics[height=3in, angle=90]{HD68_IDC_FP.pdf}
+    \includegraphics[height=3.1in, angle=90]{photo5568.jpg}
+    \includegraphics[height=2.5in, angle=90]{fp5568.jpg}
    \caption{Card and front panel}
 \end{figure}

--- a/5632.tex
+++ b/5632.tex
@ -0,0 +1,166 @@
+\input{preamble.tex}
+\input{shared/dactino.tex}
+\graphicspath{{images/5632}, {images}}
+
+\title{5632 DAC Fastino}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{32-channel fast DAC}
+        \item{16-bit resolution}
+        \item{3 MSPS per channel}
+        \item{Output voltage ±10V}
+        \item{Gateware CIC interpolation}
+        \item{HD68 connector}
+        \item{Can be broken out to BNC/SMA/MCX}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Low-frequency arbitrary waveform generation}
+        \item{Driving DC electrodes in ion traps}
+    \end{itemize}
+
+\generaldescription{5632 DAC Fastino}{slower 5432 DAC Zotino}
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.25in]{photo5632.jpg}
+    \caption{Fastino card}
+    \includegraphics[height=3in, angle=90]{fp5632.pdf}
+    \caption{Fastino front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5632 DAC Fastino}{https://github.com/sinara-hw/Fastino}
+
+\section{Electrical Specifications}
+
+    % \hypersetup{hidelinks}
+    % \urlstyle{same}
+    These specifications are based on the datasheet of the DAC IC
+    (AD5542\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf}}),
+    and various information from the Sinara wiki\footnote{\label{fastino_wiki}\url{https://github.com/sinara-hw/Fastino/wiki}}.
+
+    \begin{table}[h]
+    \centering
+    \begin{threeparttable}
+    \caption{Output Specifications}
+    \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+        \thickhline
+        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+        \textbf{Unit} & \textbf{Conditions} \\
+        Sampling rate & & 3\dag & & MSPS & per channel \\
+        \hline
+        Output voltage & -10 & & 10 & V & \\
+        \hline
+        Resolution\repeatfootnote{dac} & & 16 & & bits & \\
+        \hline
+        Settling time\repeatfootnote{dac} & & 1 & & \textmu s & \\
+        \hline
+        Temperature coefficient\repeatfootnote{fastino_wiki} & & & 7 & ppm & \\
+        \hline
+        3dB bandwidth & & 500 & & kHz & \\
+        \hline
+        Power consumption & 7 & & 13 & W & \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+    \dag Note that current QUARTIQ gateware supports 2.55 MSPS maximum.
+
+    The following table records cross-talk and transient behavior by Fastino, collected in various Sinara issues, see spur analysis\footnote{\label{fastino56}\url{https://github.com/sinara-hw/Fastino/issues/56}}, cross-talk\footnote{\url{https://github.com/sinara-hw/Fastino/issues/85}}, and noise summary\footnote{\url{https://github.com/sinara-hw/Fastino/issues/51}}. DAC output during output noise measurement was 6.875 V, updating continuously, channel 27 used for recording.
+
+    \begin{table}[h]
+    \centering
+    \begin{threeparttable}
+    \caption{Electrical Characteristics}
+    \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+        \thickhline
+        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+        \textbf{Unit} & \textbf{Conditions / Comments} \\
+        \hline
+        DC cross-talk & & & -65 & dBmV & \\
+        \hline
+        Output noise & & & & & over 1kHz bandwidth \\
+        \hspace{18mm} @ 500 kHz & & 60 & 80 & nV/rtHz & \\
+        \hspace{18mm} @ 2 MHz & & & 12 & nV/rtHz & \\
+        \hspace{18mm} @ 10 MHz & & & 4 & nV/rtHz & \\
+        \hline
+        Broadband noise & & & & & over 6.9kHz bandwidth \\
+        \hspace{18mm} @ 100 kHz & & 56 & & nV/rtHz & \\
+        \hspace{18mm} @ 1 MHz & & 14 & & nV/rtHz & \\
+        \hline
+        Spur-free range & 0.1 & & 5 & MHz & Correctly configured\repeatfootnote{fastino56} \\
+        Digital update spurs & & 560 & & nVrm & @ 2.55MHz \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+    % Is it worth recounting spur summary issue here?
+
+\newpage
+
+\section{LEDs}
+
+    5632 DAC Fastino provides eight user LEDs in the front panel. These are directly accessible with ARTIQ RTIO. Four additional LEDs indicate, respectively, power good (\texttt{PG}), FPGA done (\texttt{FD}), overtemperature (\texttt{OT}), and gateware or initialization error (\texttt{ERR}).
+
+\sysdescsection
+
+    5632 DAC Fastino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "fastino",
+                "ports": [0],
+                "log2_width": 0 // select 0 to 5, default is 0
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port used on the core device. Any port may be used on the core device side. Fastino provides two EEM ports, of which ARTIQ always requires the first, \texttt{EEM0}. The second, \texttt{EEM1}, should not be used.
+
+    The \texttt{log2\_width} field accepts a number from 0 to 5 inclusive and represents (in powers of two) the number of DAC channels packed into a single RTIO write (1 to 32). This allows and defines the use of \texttt{set\_group()} functions rather than \texttt{set\_dac()} as in examples given below.
+
+\codesectiondactino{5632 DAC Fastino}{Fastino}{fastino.py}
+
+    \subsection{CIC interpolators}
+
+    Fastino gateware features dynamically configurable CIC (cubic B-spline) interpolators, defined individually by channel, with interpolation rates from 1 (2.55 MSPS) to 65536 (39 SPS). For more details, see manual documentation on ARTIQ driver functions \texttt{stage\_cic} and \texttt{apply\_cic}.
+
+\ordersection{5632 DAC Fastino}
+
+\finalfootnote
+
+\end{document}
--- a/5716.tex
+++ b/5716.tex
@ -0,0 +1,205 @@
+\input{preamble.tex}
+\input{shared/coredevice.tex}
+\graphicspath{{images}{images/5716}}
+
+\title{5716 DAC Shuttler}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+\begin{itemize}
+    \item{16-channel DAC}
+    \item{14-bit resolution, $<1$ LSB DNL}
+    \item{125 MSPS sample rate}
+    \item{Output voltage ±10 V}
+    \item{EEM FMC carrier with Artix-7 FPGA core}
+    \item{Remote analog front end card}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Driving DC electrodes in ion traps}
+    \item{Ion chain splitting, ion shuttling}
+\end{itemize}
+
+\section{General Description}
+
+    The 5716 DAC Shuttler is an 8hp EEM module, shipped with associated remote analog front-end (AFE), part of the ARTIQ/Sinara family. It consists of the Shuttler FMC paired with an 8hp Sinara EEM FMC Carrier, which is capable of running as an ARTIQ satellite core through DRTIO-over-EEM. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+    ARTIQ gateware implements NIST PDQ-style waveform synthesizer which supports the use of sigma-delta modulation to increase effective resolution to 16 bits.
+
+    Digital communication between FMC and remote AFE is provided through mini-SAS HD cables. The AFE supports ±10 V output and 50 MHz 3dB bandwidth, using onboard 24-bit ADC for calibration.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+%
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=1.7in, angle=-90]{photo5716.jpg}
+    \caption{Shuttler FMC}
+    \includegraphics[height=1.5in]{shuttler_afe.jpg}
+    \caption{Shuttler AFE}
+    \includegraphics[height=1.5in]{fmc_side.jpg}
+    \caption{Sinara EEM FMC carrier}
+    \includegraphics[height=2.5in, angle=90]{fp5716.jpg}
+    \caption{Shuttler front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5716 DAC Shuttler}{https://github.com/sinara-hw/FMC_Shuttler} Files for the AFE card are stored at \url{https://github.com/sinara-hw/AFE_DAC_External}. Files for the Sinara EEM FMC Carrier can be found at \url{https://github.com/sinara-hw/EEM_FMC_Carrier}.
+
+\section{Electrical Specifications}
+
+    These specifications are based on the datasheet of the DAC IC (AD9117\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9114_9115_9116_9117.pdf}}), board measurements\footnote{\label{shuttler36}\url{https://github.com/sinara-hw/FMC_Shuttler/issues/36}}, and various information from the Sinara wiki\footnote{\label{wiki}\url{https://github.com/sinara-hw/FMC_Shuttler/wiki}}.
+
+    \begin{table}[h]
+        \centering
+        \begin{threeparttable}
+        \caption{Output Specifications}
+        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+            \thickhline
+            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+            \textbf{Unit} & \textbf{Conditions} \\
+            Sampling rate\repeatfootnote{wiki} & & 125 & & MSPS & \\
+            \hline
+            Output voltage\repeatfootnote{wiki} & -10 & & +10 & V & \\
+            \hline
+            Resolution\repeatfootnote{wiki} & & 14 & & bits & Raw \\
+                       & & 16 & & bits & With sigma-delta modulation \\
+            \hline
+            Settling time\repeatfootnote{dac} & & 11.5 & & ns & \\
+            \hline
+            Analog bandwidth\repeatfootnote{shuttler36} & & 12 & & MHz & \\
+            \hline
+            3dB bandwidth\repeatfootnote{wiki} & & 50 & & MHz & \\
+            \thickhline
+        \end{tabularx}
+        \end{threeparttable}
+    \end{table}
+
+    Power to Shuttler is supplied over EEM. Power to the AFE is to be supplied over a 4-pin circular M8 connector placed between the mini-SAS HD ports. The AFE output port is 25-pin DSUB.
+
+\artiqsection
+
+    The Sinara EEM FMC Carrier features an XC7A200T-3FBG484E Xilinx Artix-7 FPGA, usually configured as an ARTIQ satellite core. Firmware and gateware for the Sinara EEM FMC Carrier is closely related to that used for 1124 Kasli 2.0 satellites. The specific binary generation target can be found in the module \texttt{artiq.gateware.targets.efc} of the ARTIQ repository.
+
+\newpage
+
+\sysdescsection
+
+    5716 Shuttler should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+        {
+            "type": "shuttler",
+            "ports": 0
+        }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port number used on the core device. Any port can be used. On the other side, the Sinara EEM FMC Carrier possesses two EEM ports, but only one is necessary for Shuttler. This should always be \texttt{EEM0}.
+
+    Since Shuttler acts as a DRTIO satellite, the DRTIO type of the core device should be specified as master, not standalone, even if no other satellite cores are used. DRTIO-over-EEM for Shuttler is automatically assigned a destination number, \#4 on Kasli 2.0, \#5 on Kasli-SoC\footnote{i.e., in both cases, first available destination number after those associated with the core device's downstream SFP slots.}. Destination numbers count up correspondingly for additional Shuttlers. See the ARTIQ manual\footnote{\url{https://m-labs.hk/artiq/manual/using_drtio_subkernels.html}} for instructions on configuring a routing table, for cases where you need one (for example, a Shuttler on a DRTIO satellite).
+
+\section{Clocking}
+
+    Clock input should be provided to Shuttler through the EEM FMC Carrier. The EEM FMC Carrier \textit{must} share a clock source with the associated core device. Clocks must be aligned to utilize DRTIO-over-EEM. Clock input can be provided to EEM FMC Carrier via SMA connector on front panel or MMCX connector at back of board (top right, above \texttt{EEM0}). The Shuttler FMC features a front panel MCX connector labeled for clock input; this is currently unused by ARTIQ firmware/gateware.
+
+    \begin{multicols}{2}
+        FMC Carrier clock source must be configured by setting the DIP switches on back of the board, under the following schema:
+
+        \begin{center}
+            \begin{tabular}{ | c | c | c | } \thickhline
+            \textbf{Clock Source} & \textbf{CLK\_SEL0} & \textbf{CLK\_SEL1} \\
+            \thickhline
+            Front panel SMA & 0 & 0 \\ \hline
+            Internal oscillator & 1 & 0 \\ \hline
+            Back MMCX & 0 & 1 \\ \hline
+            PE CLK & 1 & 1 \\ \hline
+            \end{tabular}
+        \end{center}
+
+        \vspace*{\fill}
+
+    \columnbreak
+
+        \begin{center}
+            \centering
+            \includegraphics[height=1.7in]{shuttler_dip_switches.jpg}
+            \captionof{figure}{Position of DIP switches}
+        \end{center}
+
+    \end{multicols}
+
+    Users should note that PE CLK and internal oscillator are not valid source choices for Shuttler.
+
+    At first power-up, FMC Carrier and connected core device will determine the clock skew over EEM transceiver and store the result in configuration memory. It can be accessed in ARTIQ under the key \texttt{eem\_drtio\_delay0} (where \texttt{0} is a counter that will be incremented for further DRTIO-over-EEM connections.)
+
+    If EEM cable or clocking cables are changed, or if either device is reflashed for any reason, this value must be manually erased in order to force a reevaluation of the clock skew. Either \texttt{artiq\_coremgmt config remove} (for original ARTIQ) or direct access to the SD card (on Zynq) should be used.
+
+\newpage
+
+\section{LEDs}
+
+    The EEM FMC Carrier provides two user LEDs, \texttt{L0} and \texttt{L1}, located on the front panel, which are accessible in ARTIQ gateware and can be used for testing.
+
+    The Shuttler AFE provides twenty LEDs in two banks. The four-LED bank to the right of the mini-SAS connectors indicate power status. The sixteen-LED bank to the left of the mini-SAS connectors indicate output relay status. DAC output is only valid when corresponding relay LEDs are on.
+
+\codesection{5716 DAC Shuttler}
+
+    Shuttler is capable of generating a waveform in the following equation:
+
+    \[ w(t) = a(t) + b(t) * cos(c(t)) \]
+
+    where $a(t)$ and $b(t)$ are cubic splines and $c(t)$ is a quadratic spline\footnote{See also the PDQ documentation hosted at the following link: \url{https://pdq.readthedocs.io/}}.
+
+    The following code initializes relay and ADC and resets all channels.
+
+    \inputcolorboxminted{firstline=21,lastline=42}{examples/shuttler.py}
+
+\newpage
+
+    \inputcolorboxminted{firstline=43,lastline=65}{examples/shuttler.py}
+
+    \subsection{Generating a basic waveform}
+
+    The following code generates a basic sine wave of approx 10 MHz on the \texttt{DAC0 I} channel. The value of \texttt{0x147AE148} used for $c_1$ sets the frequency as $c_1 / 2^{32} * 125$ MHz.
+
+    \inputcolorboxminted{firstline=67,lastline=85}{examples/shuttler.py}
+
+    \begin{figure}[!hbt]
+        \centering
+        \includegraphics[height=3in]{sine_wave.jpg}
+        \caption{Produced waveform, measured at \texttt{AFE0} output resistor R36A, R39A.}
+    \end{figure}
+
+    For more example waveforms see also the folder \texttt{kasli\_shuttler} in the ARTIQ \texttt{examples} directory.
+
+\ordersection{5716 DAC Shuttler}
+
+\finalfootnote
+
+\end{document}
--- a/6302.tex
+++ b/6302.tex
@ -0,0 +1,120 @@
+\input{preamble.tex}
+\graphicspath{{images/6302}, {images}}
+
+\title{6302 Grabber}
+\author{M-Labs Limited}
+\date{April 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{CameraLink input interface for ARTIQ}
+        \item{Support for several EMCCD cameras}
+        \item{Low-latency image processing on-FPGA}
+        \item{Stack retrieves data sum over rectangular ROIs}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Ion fluorescence detection}
+        \item{Cold atom fluorescence detection}
+    \end{itemize}
+
+\section{General Description}
+
+The 6302 Grabber card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds frame grabber capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. 6302 Grabber targets (EM)CCD scientific cameras using the CameraLink protocol standard. Using ARTIQ gateware, incoming camera signal is immediately transferred to the carrier card, where it can be processed with low latency on-FPGA .
+
+The Sinara/ARTIQ stack supports defining rectangular ROIs (regions of interest); pixel value sums over these ROIs are reported to and can be used directly by ARTIQ kernels.
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=3in, angle=-90]{photo6302.jpg}
+    \caption{Grabber card}
+    \includegraphics[height=3in, angle=90]{fp6302.jpg}
+    \caption{Grabber front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{6302 Grabber}{https://github.com/sinara-hw/Grabber}
+
+\section{Grabber I/O}
+
+    6302 Grabber features two front-panel 26-pin MDR connectors, commonly used by CameraLink connections. Properly shielded and twisted cables intended for CameraLink should be used. For Base CameraLink, only one MDR connection (and one EEM) is necessary; higher-speed Medium CameraLink requires two.
+
+    Power over CameraLink (PoCL) is not supported.
+
+    \subsection{Grabber Single-/Double-/Triple-EEM Modes}
+
+    6302 Grabber can operate with either a single, double, or triple EEM connection to a core device. The following table specifies the connections to use and the highest CameraLink configuration supported.
+
+    \begin{table}[h]
+        \centering
+    \begin{threeparttable}
+    \begin{tabularx}{0.4\textwidth}{|l|c|c| X}
+        \hline
+        \textbf{EEMs} & \textbf{Ports} & \textbf{CameraLink} \\
+        \thickhline
+        1 & \texttt{0} & Base CameraLink\\
+        2 & \texttt{0, 1} & Medium CameraLink \\
+        3 & \texttt{0, 1, 2} & Full CameraLink \\
+        \thickhline
+    \end{tabularx}
+    \captionof{table}{Grabber EEM modes}
+    \end{threeparttable}
+    \end{table}
+
+    Note that current ARTIQ gateware only supports Base Cameralink.
+
+\sysdescsection
+
+    6302 Grabber should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "grabber",
+                "ports": [0, 1]
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 and 1 with the EEM port numbers used on the core device. Any port numbers can be used. Specifying a second port is optional. If using Grabber in single-EEM mode, specify only \texttt{[0]}.
+
+\newpage
+
+\codesectionshort{6302 Grabber card}
+
+    The following code specifies two ROIs (Regions of Interest), enables both, retrieves their accumulated data for a single frame, and disables the ROI engines.
+
+    \inputcolorboxminted{firstline=9,lastline=31}{examples/grabber.py}
+
+\ordersection{6302 Grabber}
+
+\finalfootnote
+
+\end{document}
--- a/7210.tex
+++ b/7210.tex
@ -3,8 +3,8 @@

 \title{7210 Clocker}
 \author{M-Labs Limited}
-\date{January 2024}
-\revision{Revision 3}
+\date{April 2025}
+\revision{Revision 4}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

 \begin{document}
@ -219,7 +219,7 @@ Clocker can be powered externally or internally. To provide external power, conn
 \begin{figure}[hbt!]
    \centering
    \includegraphics[height=3.5in]{photo7210.jpg}
-    \includegraphics[height=3.5in]{clocker_front_panel.jpg}
+    \includegraphics[height=3.5in]{fp7210.jpg}
    \caption{Clocker card and front panel}
 \end{figure}

--- a/2
+++ b/2
@ -10,4 +10,4 @@ $(inputs) : % : %.tex
 	rm $@.log

 clean:
-	rm -r _minted* *.aux *.out
+	rm -rf _minted* *.aux *.out
--- a/examples/fastino.py
+++ b/examples/fastino.py
@ -0,0 +1,50 @@
+from artiq.experiment import *
+from scipy import signal
+import numpy
+
+
+class Voltage(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.fastino = self.get_device("fastino")
+
+    def prepare(self):
+        self.channels = [0, 1, 2, 3]
+        self.voltages = [1.0, 2.0, 3.0, 4.0]
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.fastino.init()
+
+        delay(1*ms)
+        self.fastino.set_dac(self.voltages, self.channels)
+
+
+class TriangularWave(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.fastino = self.get_device("fastino")
+
+    def prepare(self):
+        self.period = 0.1*s
+        self.sample = 128
+        t = numpy.linspace(0, 1, self.sample)
+        self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
+        self.interval = self.period/self.sample
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.fastino.init()
+
+        delay(1*ms)
+
+        counter = 0
+        while True:
+            self.fastino.set_dac([self.voltages[counter]], [0])
+            counter = (counter + 1) % self.sample
+            delay(self.interval)
+
--- a/examples/grabber.py
+++ b/examples/grabber.py
@ -0,0 +1,27 @@
+from artiq.experiment import *
+
+
+class Grabber(EnvExperiment):
+    def build(self): 
+        self.setattr_device("core")
+        self.grabber = self.get_device("grabber")
+    
+    @kernel 
+    def run(self):
+        self.core.break_realtime()
+        delay(100*us) 
+        # setup ROI boundaries 
+        grabber.setup_roi(0, 0, 0, 2, 2) 
+        grabber.setup_roi(1, 0, 0, 2048, 2048)
+        # enable through bitwise mask 
+        mask = 0b11 
+        grabber.gate_roi(mask)
+
+        # trigger the camera
+        
+        # retrieves data from enabled ROIs 
+        n = [0] * 2 
+        grabber.input_mu(n)
+        # disable ROIs 
+        self.core.break_realtime()
+        grabber.gate_roi(0)
--- a/examples/shuttler.py
+++ b/examples/shuttler.py
@ -0,0 +1,85 @@
+from artiq.experiment import *
+
+class SineWave(EnvExperiment):
+
+    def build(self):
+        self.setattr_device("core")
+        self.shuttler0_leds = (
+            [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
+        )
+        self.setattr_device("shuttler0_config")
+        self.setattr_device("shuttler0_trigger")
+        self.shuttler0_dcbias = (
+            [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
+        )
+        self.shuttler0_dds = (
+            [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
+        )
+        self.setattr_device("shuttler0_relay")
+        self.setattr_device("shuttler0_adc")
+
+    @kernel
+    def relay_init(self):
+        self.shuttler0_relay.init()
+        self.shuttler0_relay.enable(0x0000)
+
+    @kernel
+    def adc_init(self):
+        delay_mu(int64(self.core.ref_multiplier))
+        self.shuttler0_adc.power_up()
+
+        delay_mu(int64(self.core.ref_multiplier))
+        assert self.shuttler0_adc.read_id() >> 4 == 0x038d
+
+        delay_mu(int64(self.core.ref_multiplier))
+        # The actual output voltage is limited by the hardware,
+        # the calculated calibration gain and offset.
+        # For example, if the system has a calibration gain of
+        # 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
+        # Setting a value larger than 9.43V will result in overflow.
+        self.shuttler0_adc.calibrate(
+            self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)
+
+    @kernel
+    def shuttler_channel_reset(self, ch):
+        self.shuttler0_dcbias[ch].set_waveform(
+            a0=0, a1=0, a2=0, a3=0,
+        )
+        self.shuttler0_dds[ch].set_waveform(
+            b0=0, b1=0, b2=0, b3=0,
+            c0=0, c1=0, c2=0,
+        )
+        self.shuttler0_trigger.trigger(1 << ch)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+
+        self.relay_init()
+        self.adc_init()
+
+        for i in range(16):
+            self.shuttler_channel_reset(i)
+            # To avoid RTIO Underflow
+            delay(50*us)
+
+    @kernel
+    def sine(self):
+        for i in range(2):
+            self.shuttler0_dcbias[i].set_waveform(
+                a0=0,
+                a1=0,
+                a2=0,
+                a3=0,
+            )
+            self.shuttler0_dds[i].set_waveform(
+                b0=0x0FFF,
+                b1=0,
+                b2=0,
+                b3=0,
+                c0=0,
+                c1=0x147AE148, # Frequency = 10MHz
+                c2=0,
+            )
+        self.shuttler0_trigger.trigger(0xFFFF)
--- a/examples/zotino.py
+++ b/examples/zotino.py
@ -6,7 +6,7 @@ import numpy
 class Voltage(EnvExperiment):
    def build(self):
        self.setattr_device("core")
-        self.zotino = self.get_device("zotino0")
+        self.zotino = self.get_device("zotino")

    def prepare(self):
        self.channels = [0, 1, 2, 3]
@ -25,7 +25,7 @@ class Voltage(EnvExperiment):
 class TriangularWave(EnvExperiment):
    def build(self):
        self.setattr_device("core")
-        self.zotino = self.get_device("zotino0")
+        self.zotino = self.get_device("zotino")

    def prepare(self):
        self.period = 0.1*s
@ -44,6 +44,6 @@ class TriangularWave(EnvExperiment):

        counter = 0
        while True:
-            self.zotino.set_dac([self.voltages[counter]], [0])
+            self.zotino.write_dac([self.voltages[counter]], [0])
            counter = (counter + 1) % self.sample
            delay(self.interval)
--- a/flake.lock
+++ b/flake.lock
@ -2,16 +2,16 @@
  "nodes": {
    "nixpkgs": {
      "locked": {
-        "lastModified": 1729880355,
-        "narHash": "sha256-RP+OQ6koQQLX5nw0NmcDrzvGL8HDLnyXt/jHhL1jwjM=",
+        "lastModified": 1744440957,
+        "narHash": "sha256-FHlSkNqFmPxPJvy+6fNLaNeWnF1lZSgqVCl/eWaJRc4=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "18536bf04cd71abd345f9579158841376fdd0c5a",
+        "rev": "26d499fc9f1d567283d5d56fcf367edd815dba1d",
        "type": "github"
      },
      "original": {
        "owner": "NixOS",
-        "ref": "nixos-unstable",
+        "ref": "nixos-24.11",
        "repo": "nixpkgs",
        "type": "github"
      }
--- a/flake.nix
+++ b/flake.nix
@ -1,7 +1,7 @@
 {
  description = "Sinara datasheets";

-  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.11;

  outputs = { self, nixpkgs }:
    let
--- a/images/1008/fp1008.pdf
+++ b/images/1008/fp1008.pdf
--- a/images/1008/photo1008.jpg
+++ b/images/1008/photo1008.jpg
--- a/images/1124/Kasli_FP.pdf
+++ b/images/1124/Kasli_FP.pdf
--- a/images/1124/fp1124.jpg
+++ b/images/1124/fp1124.jpg
--- a/images/1125/Kasli-SoC_FP.pdf
+++ b/images/1125/Kasli-SoC_FP.pdf
--- a/images/1125/fp1125.jpg
+++ b/images/1125/fp1125.jpg
--- a/images/1125/kasli-soc_dip_switches.jpg
+++ b/images/1125/kasli-soc_dip_switches.jpg
--- a/images/1125/kasli_soc_dip_switches.jpg
+++ b/images/1125/kasli_soc_dip_switches.jpg
--- a/images/1550/fp1550.pdf
+++ b/images/1550/fp1550.pdf
--- a/images/1550/kirdy_gui.jpg
+++ b/images/1550/kirdy_gui.jpg
--- a/images/1550/kirdy_imp_switch.jpg
+++ b/images/1550/kirdy_imp_switch.jpg
--- a/images/1550/kirdy_mod_switch.jpg
+++ b/images/1550/kirdy_mod_switch.jpg
--- a/images/1550/photo1550.jpg
+++ b/images/1550/photo1550.jpg
--- a/images/2238/fp2238.jpg
+++ b/images/2238/fp2238.jpg
--- a/images/4456-4457/fp4456.jpg
+++ b/images/4456-4457/fp4456.jpg
--- a/images/4456-4457/fp4456.pdf
+++ b/images/4456-4457/fp4456.pdf
--- a/images/4456-4457/fp4457.jpg
+++ b/images/4456-4457/fp4457.jpg
--- a/images/4456-4457/mirny_phase_noise_cm_choke.png
+++ b/images/4456-4457/mirny_phase_noise_cm_choke.png
--- a/images/4456-4457/mirny_phase_noise_frequency.png
+++ b/images/4456-4457/mirny_phase_noise_frequency.png
--- a/images/4456-4457/photo4456.jpg
+++ b/images/4456-4457/photo4456.jpg
--- a/images/4456-4457/photo4457.jpg
+++ b/images/4456-4457/photo4457.jpg
--- a/images/5568/HD68_IDC_FP.pdf
+++ b/images/5568/HD68_IDC_FP.pdf
--- a/images/5568/fp5568.jpg
+++ b/images/5568/fp5568.jpg
--- a/images/5632/fp5632.pdf
+++ b/images/5632/fp5632.pdf
--- a/images/5632/photo5632.jpg
+++ b/images/5632/photo5632.jpg
--- a/images/5716/fmc_side.jpg
+++ b/images/5716/fmc_side.jpg
--- a/images/5716/fp5716.jpg
+++ b/images/5716/fp5716.jpg
--- a/images/5716/photo5716.jpg
+++ b/images/5716/photo5716.jpg
--- a/images/5716/shuttler_afe.jpg
+++ b/images/5716/shuttler_afe.jpg
--- a/images/5716/shuttler_dip_switches.jpg
+++ b/images/5716/shuttler_dip_switches.jpg
--- a/images/5716/sine_wave.jpg
+++ b/images/5716/sine_wave.jpg
--- a/images/6302/fp6302.jpg
+++ b/images/6302/fp6302.jpg
--- a/images/6302/fp6302.pdf
+++ b/images/6302/fp6302.pdf
--- a/images/6302/photo6302.jpg
+++ b/images/6302/photo6302.jpg
--- a/images/7210/clocker_front_panel.jpg
+++ b/images/7210/clocker_front_panel.jpg
--- a/preamble.tex
+++ b/preamble.tex
@ -58,6 +58,14 @@ The sections below demonstrate simple usage scenarios of extensions on the ARTIQ
 The full documentation for ARTIQ software and gateware, including guides for their use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
 }

+\newcommand{\codesectionshort}[1]{
+\section{Example ARTIQ Code}
+
+The code below demonstrates a simple usage scenario of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. Not all features of the ARTIQ system are shown.
+
+The full documentation for ARTIQ software and gateware, including guides for their use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
+}
+
 \newcommand*{\ordersection}[1]{
 \section{Ordering Information}
 To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
--- a/shared/dactino.tex
+++ b/shared/dactino.tex
@ -0,0 +1,33 @@
+\newcommand{\generaldescription}[2] {
+
+    \section{General Description}
+
+    The #1 is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It is closely related to the #2 and the two cards share a compatible output interface.
+
+    It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
+
+    Output voltage can be amplified to ±50V with the 32-channel Sinara 5633 HV Amplifier mezzanine, which provides an identical output interface.
+}
+
+\newcommand{\codesectiondactino}[3] {
+
+    \codesection{#1}
+
+    \subsection{Setting output voltage}
+
+    The following example initializes the #2 card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltage of all 4 channels is updated simultaneously with the use of \texttt{set\char`_dac()}.
+
+    \inputcolorboxminted{firstline=11,lastline=22}{examples/#3}
+
+    % this new page works for both datasheets, but may not if sections are added
+\newpage
+
+    \subsection{Triangular wave}
+
+    The following example generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+
+    Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
+
+    \inputcolorboxminted{firstline=30,lastline=49}{examples/#3}
+
+}
--- a/shared/suservo.tex
+++ b/shared/suservo.tex
@ -0,0 +1,87 @@
+
+\section{ARTIQ SU-Servo}
+
+    ARTIQ also allows for the joint configuration of one or two 4410 DDS Urukul cards and a 5108 Sampler as an integrated servo for laser intensity stabilization and similar purposes. SU-Servo also supports other additional features, such as preconfigured profiles per channel and automatic integrator hold. Urukuls must be 4410 AD9910 variants (not 4412 AD9912) and set to SU-Servo mode by DIP switch.
+
+\subsection{SU-Servo System Description Entry}
+
+    SU-Servo should be entered in the peripherals list of the corresponding core device in a single entry in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "suservo",
+                "sampler_ports": [0, 1],
+                "urukul0_ports": [2, 3],
+                "urukul1_ports": [4, 5], // optional
+                "clk_sel": 2 // select 0 to 2
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Enter the actual EEM port numbers used on the core device. Any ports can be used. If using only one Urukul (and half of the available Sampler channels), the \texttt{urukul1\_ports} field may be left out entirely.
+
+    For the \texttt{clk\_sel} field, \texttt{0} represents the internal 100 MHz oscillator, \texttt{1} represents SMA input, and \texttt{2} represents MMCX input.
+
+% miraculously, this newpage is good for both Sampler and Urukul datasheets!
+% will probably break if any sections are added though
+\newpage
+
+\section{Example SU-Servo Code}
+
+    In SU-Servo configuration, amplitude of the Urukul DDS output can be controlled with the Sampler ADC input through PI control, characterised by the following transfer function:
+
+    \[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
+
+    In the following example, the DDS amplitude is set proportionally to the ADC input from Sampler. We initialize SU-Servo and all channels first. Note that the programmable gain of the Sampler is $10^0=1$ and the input range is [-10V, 10V].
+
+    \inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
+
+    Next, we set up the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
+
+    \inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
+
+    Then, configure the DDS frequency to 10 MHz with 3V input offset. When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
+
+    \inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
+
+    SU-Servo encodes the ADC voltage on a linear scale [-1, 1]. Therefore, 3V is converted to 0.3. Note that the ASF of all DDS channels ss capped at 1.0 and the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
+
+    Finally, enable the SU-Servo channel with the IIR filter programmed beforehand:
+
+    \inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
+
+    A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC. The RMS voltage of the DDS channel against the ADC voltage is plotted. The DDS channel is terminated with 50\textOmega.
+
+    \begin{center}
+    \begin{tikzpicture}[
+        declare function={
+            func(\x)= and(\x>=-10, \x<-7) * (160) +
+                and(\x>=-7, \x<3) * (16*(3-x)) +
+                and(\x>=3, \x<10) * (0);
+        }
+    ]
+    \begin{axis}[
+        axis x line=middle, axis y line=middle,
+        every axis x label/.style={
+            at={(axis description cs:0.5,-0.1)},
+            anchor=north,
+        },
+        every axis y label/.style={
+            at={(ticklabel* cs:1.05)},
+            anchor=south,
+        },
+        minor x tick num=3,
+        grid=both,
+        height=8cm,
+        width=12cm,
+        ymin=-5, ymax=180, ytick={0,16,...,160}, ylabel=DDS RMS Voltage ($mV_{rms}$),
+        xmin=-10, xmax=10, xtick={-10,-8,...,10}, xlabel=Sampler Voltage ($V$),
+    ]
+
+    \addplot[very thick, blue, samples=21, domain=-10:10]{func(x)};
+    \end{axis}
+    \end{tikzpicture}
+    \end{center}
+
+    DDS signal should be attenuated. High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power. 15 dB attenuation at the digital attenuator was applied in this example.
Author	SHA1	Message	Date
architeuthis	e2beb57e73	5432/5632: fixes	2025-04-21 20:29:02 +02:00
architeuthis	5c60149665	5432/5632: add HVAmp note	2025-04-21 20:29:02 +02:00
architeuthis	31c7fdade7	5632: init	2025-04-21 20:29:02 +02:00
architeuthis	2bbe3ee6a9	5432: bump revision number	2025-04-21 20:29:02 +02:00
architeuthis	05f2d8062c	5432: unify with fastino	2025-04-21 20:29:02 +02:00
architeuthis	4293a80cdc	zotino/fastino: shared sections	2025-04-21 20:29:02 +02:00
architeuthis	2232c2ef8b	5432: add LED note	2025-04-21 20:29:02 +02:00
architeuthis	6d1d22dbe6	5432: add sysdesc section	2025-04-21 20:29:02 +02:00
architeuthis	7a9322ad01	5432: formatting	2025-04-21 20:29:02 +02:00
Sebastien Bourdeauducq	8e7316527c	bump revisions (2)	2025-04-17 17:06:53 +01:00
Sebastien Bourdeauducq	d77fbf638f	bump revisions	2025-04-17 17:06:03 +01:00
architeuthis	04754d66b3	2238: add front panel photo	2025-04-18 00:01:50 +08:00
architeuthis	a696cdc7ac	6302: add front panel/update top photo	2025-04-18 00:01:50 +08:00
architeuthis	3657bc76d7	7210: standardize fp file name	2025-04-18 00:01:50 +08:00
architeuthis	a22c6e6957	5568: add front panel photo	2025-04-18 00:01:50 +08:00
architeuthis	2175218c20	4456-4457: add front panel photos	2025-04-18 00:01:50 +08:00
architeuthis	789c7a2c81	1125: add front panel/top photos	2025-04-18 00:01:50 +08:00
architeuthis	1a8bdf60ad	1124: add front panel photo	2025-04-18 00:01:50 +08:00
Sebastien Bourdeauducq	0be9a0a490	flake: switch to nixpkgs 24.11	2025-04-17 16:51:46 +01:00
Sebastien Bourdeauducq	1f9cc1ac4f	Makefile: don't fail if already clean	2025-04-17 16:47:58 +01:00
Sebastien Bourdeauducq	3ff9efb27d	5716: correct routing table info	2025-04-17 16:26:32 +01:00
architeuthis	f7bcb9efbb	5716: correct clock skew reset info	2025-04-17 23:23:25 +08:00
architeuthis	10714d4ccb	5716: image updates	2025-04-17 23:23:25 +08:00
architeuthis	8c01650a29	5716: fixes	2025-04-17 23:23:25 +08:00
architeuthis	d983cab68e	gitignore: unused/reference examples	2025-04-17 23:23:25 +08:00
architeuthis	26f64e2eb6	5716: init	2025-04-17 23:23:25 +08:00
Sébastien Bourdeauducq	37ac9d34e8	1550: edit	2025-04-10 12:53:05 +08:00
architeuthis	de05fb4b16	1550: Add autotune note	2025-04-10 12:13:09 +08:00
architeuthis	de910e5e1a	1550: further fixes	2025-04-10 12:13:09 +08:00
architeuthis	ccdbe32bbe	1550: typo	2025-04-10 12:13:09 +08:00
architeuthis	a4139d5e7f	1550: add termination switch section	2025-04-10 12:13:09 +08:00
architeuthis	6f23469583	1550: rehaul specification table	2025-04-10 12:13:09 +08:00
architeuthis	de0c310da9	1550: fix typo	2025-04-10 12:13:09 +08:00
architeuthis	6f32150571	1550: images update	2025-04-10 12:13:09 +08:00
architeuthis	b5b1643ef5	1550: init	2025-04-10 12:13:09 +08:00
architeuthis	e1b3a82815	4410-4412: Note on multi-chip synchronisation	2025-03-30 13:34:50 +02:00
architeuthis	a7c1dee8b6	4410-4412/suservo: add clk_sel details	2025-03-29 17:17:21 +08:00
architeuthis	b0e763336e	4410-4412: add 'Model comparison', fix double EEM section	2025-03-29 17:17:21 +08:00
architeuthis	ffafafe617	5108: fix typo	2025-03-29 17:17:21 +08:00
architeuthis	136d113f28	4410-4412: fixes	2025-03-29 17:17:21 +08:00
architeuthis	7782184723	5108: bump revision number	2025-03-29 17:17:21 +08:00
architeuthis	19d0e4e421	4410-4412: bump revision number	2025-03-29 17:17:21 +08:00
architeuthis	2070147150	4410-4412: LED section	2025-03-29 17:17:21 +08:00
architeuthis	686b5aec03	5108: sysdesc section and SUServo	2025-03-29 17:17:21 +08:00
architeuthis	f8b3290d3e	4410-4412: sysdesc section and SUServo	2025-03-29 17:17:21 +08:00
architeuthis	f9d962db69	suservo: shared file	2025-03-29 17:17:21 +08:00
architeuthis	77d0001542	5108: formatting	2025-03-29 17:17:21 +08:00
architeuthis	42f55a2779	4410-4412: formatting	2025-03-29 17:17:21 +08:00
architeuthis	f3f97ea529	4456-4457: correct AD535x discrepancy	2025-03-29 17:15:02 +08:00
architeuthis	f422666af9	4456-4457: fixes	2025-03-29 17:15:02 +08:00
architeuthis	c9e5210757	4456-4457: add note on LEDs	2025-03-29 17:15:02 +08:00
architeuthis	1eb306e444	4456 -> 4456-4457: add almazny	2025-03-29 17:15:02 +08:00
architeuthis	89d7e84e3f	6302: fixes	2025-03-25 13:53:40 +01:00
architeuthis	511974f0ce	6302: init	2025-03-22 20:34:49 +01:00
architeuthis	3297108ca9	1008: init	2025-02-23 10:45:17 +01:00