datasheets/5716.tex

\input{preamble.tex}
\input{shared/coredevice.tex}
\graphicspath{{images}{images/5716}}

\title{5716 DAC Shuttler}
\author{M-Labs Limited}
\date{January 2025}
\revision{Revision 1}
\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}

\begin{document}
\maketitle

\section{Features}
\begin{itemize}
    \item{16-channel DAC}
    \item{14-bit resolution, $<1$ LSB DNL}
    \item{125 MSPS sample rate}
    \item{Output voltage ±10 V}
    \item{EEM FMC carrier with Artix-7 FPGA core}
    \item{Remote analog front end card}
\end{itemize}

\section{Applications}

\begin{itemize}
    \item{Driving DC electrodes in ion traps}
    \item{Ion chain splitting, ion shuttling}
\end{itemize}

\section{General Description}

    The 5716 DAC Shuttler is an 8hp EEM module, shipped with associated remote analog front-end (AFE), part of the ARTIQ/Sinara family. It consists of the Shuttler FMC paired with an 8hp Sinara EEM FMC Carrier, which is capable of running as an ARTIQ satellite core through DRTIO-over-EEM. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.

    ARTIQ gateware implements NIST PDQ-style waveform synthesizer which supports the use of sigma-delta modulation to increase effective resolution to 16 bits.

    Digital communication between FMC and remote AFE is provided through mini-SAS HD cables. The AFE supports ±10 V output and 50 MHz 3dB bandwidth, using onboard 24-bit ADC for calibration.

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\begin{figure}[hbt!]
    \centering
    \includegraphics[height=1.7in, angle=-90]{photo5716.jpg}
    \caption{Shuttler FMC}
    \includegraphics[height=1.5in]{shuttler_afe.jpg}
    \caption{Shuttler AFE}
    \includegraphics[height=1.5in]{fmc_side.jpg}
    \caption{Sinara EEM FMC carrier}
    \includegraphics[height=2.5in, angle=90]{fp5716.jpg}
    \caption{Shuttler front panel}
\end{figure}

% For wide tables, a single column layout is better. It can be switched
% page-by-page.
\onecolumn

\sourcesection{5716 DAC Shuttler}{https://github.com/sinara-hw/FMC_Shuttler} Files for the AFE card are stored at \url{https://github.com/sinara-hw/AFE_DAC_External}. Files for the Sinara EEM FMC Carrier can be found at \url{https://github.com/sinara-hw/EEM_FMC_Carrier}.

\section{Electrical Specifications}

    These specifications are based on the datasheet of the DAC IC (AD9117\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD9114_9115_9116_9117.pdf}}), board measurements\footnote{\label{shuttler36}\url{https://github.com/sinara-hw/FMC_Shuttler/issues/36}}, and various information from the Sinara wiki\footnote{\label{wiki}\url{https://github.com/sinara-hw/FMC_Shuttler/wiki}}.

    \begin{table}[h]
        \centering
        \begin{threeparttable}
        \caption{Output Specifications}
        \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
            \thickhline
            \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
            \textbf{Unit} & \textbf{Conditions} \\
            Sampling rate\repeatfootnote{wiki} & & 125 & & MSPS & \\
            \hline
            Output voltage\repeatfootnote{wiki} & -10 & & +10 & V & \\
            \hline
            Resolution\repeatfootnote{wiki} & & 14 & & bits & Raw \\
                       & & 16 & & bits & With sigma-delta modulation \\
            \hline
            Settling time\repeatfootnote{dac} & & 11.5 & & ns & \\
            \hline
            Analog bandwidth\repeatfootnote{shuttler36} & & 12 & & MHz & \\
            \hline
            3dB bandwidth\repeatfootnote{wiki} & & 50 & & MHz & \\
            \thickhline
        \end{tabularx}
        \end{threeparttable}
    \end{table}

    Power to Shuttler is supplied over EEM. Power to the AFE is to be supplied over a 4-pin circular M8 connector placed between the mini-SAS HD ports. The AFE output port is 25-pin DSUB.

\artiqsection

    The Sinara EEM FMC Carrier features an XC7A200T-3FBG484E Xilinx Artix-7 FPGA, usually configured as an ARTIQ satellite core. Firmware and gateware for the Sinara EEM FMC Carrier is closely related to that used for 1124 Kasli 2.0 satellites. The specific binary generation target can be found in the module \texttt{artiq.gateware.targets.efc} of the ARTIQ repository.

\newpage

\sysdescsection

    5716 Shuttler should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:

    \begin{tcolorbox}[colback=white]
        \begin{minted}{json}
        {
            "type": "shuttler",
            "ports": 0
        }
        \end{minted}
    \end{tcolorbox}

    Replace 0 with the EEM port number used on the core device. Any port can be used. On the other side, the Sinara EEM FMC Carrier possesses two EEM ports, but only one is necessary for Shuttler. This should always be \texttt{EEM0}.

    Since Shuttler acts as a DRTIO satellite, the DRTIO type of the core device should be specified as master, not standalone, even if no other satellite cores are used. DRTIO-over-EEM for Shuttler is automatically assigned a destination number, \#4 on Kasli 2.0, \#5 on Kasli-SoC\footnote{i.e., in both cases, first available destination number after those associated with the core device's downstream SFP slots.}. Destination numbers count up correspondingly for additional Shuttlers. See the ARTIQ manual\footnote{\url{https://m-labs.hk/artiq/manual/using_drtio_subkernels.html}} for instructions on configuring a routing table, for cases where you need one (for example, a Shuttler on a DRTIO satellite).

\section{Clocking}

    Clock input should be provided to Shuttler through the EEM FMC Carrier. The EEM FMC Carrier \textit{must} share a clock source with the associated core device. Clocks must be aligned to utilize DRTIO-over-EEM. Clock input can be provided to EEM FMC Carrier via SMA connector on front panel or MMCX connector at back of board (top right, above \texttt{EEM0}). The Shuttler FMC features a front panel MCX connector labeled for clock input; this is currently unused by ARTIQ firmware/gateware.

    \begin{multicols}{2}
        FMC Carrier clock source must be configured by setting the DIP switches on back of the board, under the following schema:

        \begin{center}
            \begin{tabular}{ | c | c | c | } \thickhline
            \textbf{Clock Source} & \textbf{CLK\_SEL0} & \textbf{CLK\_SEL1} \\
            \thickhline
            Front panel SMA & 0 & 0 \\ \hline
            Internal oscillator & 1 & 0 \\ \hline
            Back MMCX & 0 & 1 \\ \hline
            PE CLK & 1 & 1 \\ \hline
            \end{tabular}
        \end{center}

        \vspace*{\fill}

    \columnbreak

        \begin{center}
            \centering
            \includegraphics[height=1.7in]{shuttler_dip_switches.jpg}
            \captionof{figure}{Position of DIP switches}
        \end{center}

    \end{multicols}

    Users should note that PE CLK and internal oscillator are not valid source choices for Shuttler.

    At first power-up, FMC Carrier and connected core device will determine the clock skew over EEM transceiver and store the result in configuration memory. It can be accessed in ARTIQ under the key \texttt{eem\_drtio\_delay0} (where \texttt{0} is a counter that will be incremented for further DRTIO-over-EEM connections.)

    If EEM cable or clocking cables are changed, or if either device is reflashed for any reason, this value must be manually erased in order to force a reevaluation of the clock skew. Either \texttt{artiq\_coremgmt config remove} (for original ARTIQ) or direct access to the SD card (on Zynq) should be used.

\newpage

\section{LEDs}

    The EEM FMC Carrier provides two user LEDs, \texttt{L0} and \texttt{L1}, located on the front panel, which are accessible in ARTIQ gateware and can be used for testing.

    The Shuttler AFE provides twenty LEDs in two banks. The four-LED bank to the right of the mini-SAS connectors indicate power status. The sixteen-LED bank to the left of the mini-SAS connectors indicate output relay status. DAC output is only valid when corresponding relay LEDs are on.

\codesection{5716 DAC Shuttler}

    Shuttler is capable of generating a waveform in the following equation:

    \[ w(t) = a(t) + b(t) * cos(c(t)) \]

    where $a(t)$ and $b(t)$ are cubic splines and $c(t)$ is a quadratic spline\footnote{See also the PDQ documentation hosted at the following link: \url{https://pdq.readthedocs.io/}}.

    The following code initializes relay and ADC and resets all channels.

    \inputcolorboxminted{firstline=21,lastline=42}{examples/shuttler.py}

\newpage

    \inputcolorboxminted{firstline=43,lastline=65}{examples/shuttler.py}

    \subsection{Generating a basic waveform}

    The following code generates a basic sine wave of approx 10 MHz on the \texttt{DAC0 I} channel. The value of \texttt{0x147AE148} used for $c_1$ sets the frequency as $c_1 / 2^{32} * 125$ MHz.

    \inputcolorboxminted{firstline=67,lastline=85}{examples/shuttler.py}

    \begin{figure}[!hbt]
        \centering
        \includegraphics[height=3in]{sine_wave.jpg}
        \caption{Produced waveform, measured at \texttt{AFE0} output resistor R36A, R39A.}
    \end{figure}

    For more example waveforms see also the folder \texttt{kasli\_shuttler} in the ARTIQ \texttt{examples} directory.

\ordersection{5716 DAC Shuttler}

\finalfootnote

\end{document}