forked from sinara-hw/datasheets
1124: add insn for clock configuation setup
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1124.tex
6
1124.tex
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@ -273,6 +273,12 @@ Kasli 2.0 supports a set of clock systhesizing options for the (D)RTIO system:
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Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
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Alternatively, the clock synthesizer can be bypassed using the \texttt{ext0\char`_bypass} clocking option, where the RTIO clock is directly supplied to the SMA connector.
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The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
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The resulting clock signal is then routed to both the RTIO system and downstream DRTIO satellites.
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Clocking options should be configured by setting the value of the \texttt{rtio} key to the desired configuration through \texttt{artiq\char`_coremgmt}.
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For example, the RTIO frequency is synthesized from the external 10 MHz from the SMA connector after issuing the following command.
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\begin{minted}{bash}
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artiq_coremgmt config write -s rtio ext0_synth0_10to125
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\end{minted}
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\subsection{DRTIO Satellite}
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\subsection{DRTIO Satellite}
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The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
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The RTIO clock is first recovered from the SFP transceiver connected to the upstream device. The signal is then cleaned by Si5324 clock synthesizer.
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The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
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The resulting clock signal is then routed to the RTIO system and downstream DRTIO satellties.
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