forked from sinara-hw/datasheets
4410-4412: update set() parameters
Note that the `frequency` param is mandatory in AD9912.set(), while optional in AD9910.set()
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@ -428,8 +428,7 @@ def run(self):
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_att(6.)
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self.dds0.set(10*MHz, amplitude=1.0)
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self.dds0.set(10*MHz)
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\end{minted}
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If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
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@ -449,8 +448,8 @@ def run(self):
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_att(6.)
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self.dds0.set(10*MHz, phase=0.0)
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self.dds1.set(10*MHz, phase=0.25) # 0.25 turns phase offset
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self.dds0.set(frequency=10*MHz, phase=0.0)
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self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
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\end{minted}
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Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
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It can be negated by adjusting the \texttt{phase} parameter.
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@ -487,7 +486,7 @@ def configure_ram_mode(self, dds):
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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dds.set(10*MHz, profile=-1)
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dds.set(frequency=10*MHz, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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@ -523,7 +522,7 @@ Multiple RAM channels can also be synchronized.
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Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
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For example, set phase to 0 for the channels (\texttt{phase=0.0}).
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\begin{minted}{python}
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dds.set(10*MHz, phase=0.0, profile=-1)
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dds.set(frequency=10*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
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\end{minted}
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Then, replace the \texttt{run()} function with the following.
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\begin{minted}{python}
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