4410-4412: update set() parameters

Note that the `frequency` param is mandatory in AD9912.set(), while optional in AD9910.set()
This commit is contained in:
occheung 2021-12-08 12:17:22 +08:00
parent b9c7dcec67
commit 2127697fe6

View File

@ -428,8 +428,7 @@ def run(self):
self.cpld.init()
self.dds0.init()
self.dds0.cfg_sw(True)
self.dds0.set_att(6.)
self.dds0.set(10*MHz, amplitude=1.0)
self.dds0.set(10*MHz)
\end{minted}
If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
@ -449,8 +448,8 @@ def run(self):
self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
self.dds1.set_att(6.)
self.dds0.set(10*MHz, phase=0.0)
self.dds1.set(10*MHz, phase=0.25) # 0.25 turns phase offset
self.dds0.set(frequency=10*MHz, phase=0.0)
self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
\end{minted}
Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
It can be negated by adjusting the \texttt{phase} parameter.
@ -487,7 +486,7 @@ def configure_ram_mode(self, dds):
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
dds.set(10*MHz, profile=-1)
dds.set(frequency=10*MHz, ram_destination=RAM_DEST_ASF)
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
@ -523,7 +522,7 @@ Multiple RAM channels can also be synchronized.
Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
For example, set phase to 0 for the channels (\texttt{phase=0.0}).
\begin{minted}{python}
dds.set(10*MHz, phase=0.0, profile=-1)
dds.set(frequency=10*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
\end{minted}
Then, replace the \texttt{run()} function with the following.
\begin{minted}{python}