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migen: move add extension into build

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This commit is contained in:
occheung 2020-09-17 12:59:22 +08:00
parent e834e6fcea
commit c084da1848
2 changed files with 17 additions and 25 deletions
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18
examples/fpga_config.rs
View File

@ -3,20 +3,12 @@
extern crate log; extern crate log;
use log::debug; use log::debug;
use stm32h7xx_hal::{pac, prelude::*, spi};
use stm32h7xx_hal::hal::digital::v2::{
InputPin,
OutputPin,
};
use stm32h7xx_hal::{gpio::Speed, pac, prelude::*, spi};
use cortex_m; use cortex_m;
use cortex_m::asm::nop; use cortex_m::asm::nop;
use cortex_m_rt::entry; use cortex_m_rt::entry;
use core::ptr;
use nb::block;
use firmware::flash::flash_ice40_fpga; use firmware::flash::flash_ice40_fpga;
#[path = "util/logger.rs"] #[path = "util/logger.rs"]
@ -42,7 +34,7 @@ fn main() -> ! {
logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM); logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
} }
let mut delay = cp.SYST.delay(ccdr.clocks); let delay = cp.SYST.delay(ccdr.clocks);
let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA); let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB); let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
@ -61,14 +53,14 @@ fn main() -> ! {
let fpga_sdi = gpiob.pb5.into_alternate_af5(); let fpga_sdi = gpiob.pb5.into_alternate_af5();
// Setup SPI_SS_B and CRESET_B // Setup SPI_SS_B and CRESET_B
let mut fpga_ss = gpioa.pa4.into_push_pull_output(); let fpga_ss = gpioa.pa4.into_push_pull_output();
let mut fpga_creset = gpiof.pf3.into_open_drain_output(); let fpga_creset = gpiof.pf3.into_open_drain_output();
// Setup CDONE // Setup CDONE
let fpga_cdone = gpiod.pd15.into_pull_up_input(); let fpga_cdone = gpiod.pd15.into_pull_up_input();
// Setup SPI interface // Setup SPI interface
let mut fpga_cfg_spi = dp.SPI1.spi( let fpga_cfg_spi = dp.SPI1.spi(
(fpga_sck, fpga_sdo, fpga_sdi), (fpga_sck, fpga_sdo, fpga_sdi),
spi::MODE_3, spi::MODE_3,
12.mhz(), 12.mhz(),

24
migen/fpga_config.py
View File

@ -1,24 +1,26 @@
# Import built in I/O, Connectors & Platform template for Humpback # Import built in I/O, Connectors & Platform template for Humpback
from migen.build.platforms.sinara import humpback from migen.build.platforms.sinara import humpback
# Import migen platform for Lattice Products
from migen.build.lattice import LatticePlatform
# Import migen pin record structure # Import migen pin record structure
from migen.build.generic_platform import * from migen.build.generic_platform import *
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.fhdl.specials import Instance from migen.fhdl.specials import Instance
from migen.genlib.io import * from migen.genlib.io import *
from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
from migen.genlib.io import DifferentialInput
spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
io_update = [
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
]
class UrukulConnector(Module): class UrukulConnector(Module):
def __init__(self, platform): def __init__(self, platform):
# Include extension
spi_cs = [
("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
]
io_update = [
("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
]
# Add extensions
platform.add_extension(spi_cs)
platform.add_extension(io_update)
# Request EEM I/O & SPI # Request EEM I/O & SPI
eem0 = [ eem0 = [
platform.request("eem0", 0), platform.request("eem0", 0),
@ -82,6 +84,4 @@ class UrukulConnector(Module):
if __name__ == "__main__": if __name__ == "__main__":
platform = humpback.Platform() platform = humpback.Platform()
platform.add_extension(spi_cs)
platform.add_extension(io_update)
platform.build(UrukulConnector(platform)) platform.build(UrukulConnector(platform))