dds: add cfg1 enum

src/config_register.rs

@@ -85,7 +85,7 @@ where
 	 */
 	pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
 		match self.set_all_configurations() {
-			Ok(val) => Ok(((val & status_type.get_bitmask()) >> status_type.get_shift()) as u8),
+			Ok(val) => Ok(status_type.get_filtered_content(val) as u8),
 			Err(e) => Err(e),
 		}
 	}

src/dds.rs

@@ -2,6 +2,30 @@ use embedded_hal::blocking::spi::Transfer;
 use cortex_m_semihosting::hprintln;
 use crate::Error;
 
+construct_bitmask!(CFR1Mask; u32;
+	LSB_FIRST,						0,	1,
+	SDIO_IN_ONLY,					1,	1,
+	EXT_POWER_DOWN_CTRL,			3,	1,
+	AUX_DAC_POWER_DOWN,				4,	1,
+	REFCLK_IN_POWER_DOWN,			5,	1,
+	DAC_POWER_DOWN,					6,	1,
+	DIGITAL_POWER_DOWN,				7,	1,
+	SEL_AUTO_OSK,					8,	1,
+	OSK_ENABLE,						9,	1,
+	LOAD_ARR_IO_UPDATE,				10,	1,
+	CLEAR_PHASE_ACU,				11,	1,
+	CLEAR_DIGITAL_RAMP_ACU,			12,	1,
+	AUTOCLEAR_PHASE_ACU,			13,	1,
+	AUTOCLEAR_DIGITAL_RAMP_ACU,		14,	1,
+	LOAD_LRR_IO_UPDATE,				15,	1,
+	SEL_DDS_SIN_OUT,				16,	1,
+	PROFILE_CTRL,					17,	4,
+	INV_SINC_FILTER_ENABLE,			22,	1,
+	MANUAL_OSK_EXT_CTRL,			23,	1,
+	RAM_PLAYBACK_DST,				29,	2,
+	RAM_ENABLE,						31,	1
+);
+
 pub struct DDS<SPI> {
 	spi: SPI,
 }