forked from M-Labs/humpback-dds
dds: closure param for ram set
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parent
25f8363e54
commit
883e821794
135
src/dds.rs
135
src/dds.rs
@ -64,7 +64,7 @@ construct_bitmask!(DDSCFRMask; u32;
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const WRITE_MASK :u8 = 0x00;
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const READ_MASK :u8 = 0x80;
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#[derive(Clone)]
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#[derive(Clone, PartialEq)]
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pub enum RAMDestination {
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Frequency = 0,
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Phase = 1,
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@ -355,14 +355,9 @@ where
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assert!(phase_offset >= 0.0 && phase_offset < 360.0);
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assert!(amp_scale_factor >=0.0 && amp_scale_factor <= 1.0);
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let resolutions :[u64; 3] = [1 << 32, 1 << 16, 1 << 14];
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let ftw = ((resolutions[0] as f64) * f_out / self.f_sys_clk) as u32;
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let pow = ((resolutions[1] as f64) * phase_offset / 360.0) as u16;
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let asf :u16 = if amp_scale_factor == 1.0 {
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0x3FFF
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} else {
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((resolutions[2] as f64) * amp_scale_factor) as u16
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};
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let ftw = self.frequency_to_ftw(f_out);
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let pow = self.degree_to_pow(phase_offset);
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let asf = self.amplitude_to_asf(amp_scale_factor);
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// Setup configuration registers before writing single tone register
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self.enable_single_tone_configuration()?;
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@ -390,9 +385,7 @@ where
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// Setup configuration registers before writing single tone register
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self.enable_single_tone_configuration()?;
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// Calculate frequency tuning work (FTW)
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let f_res: u64 = 1 << 32;
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let ftw = ((f_res as f64) * f_out / self.f_sys_clk) as u32;
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let ftw = self.frequency_to_ftw(f_out);
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// Read existing amplitude/phase data
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let mut register: [u8; 8] = [0; 8];
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@ -418,9 +411,7 @@ where
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// Setup configuration registers before writing single tone register
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self.enable_single_tone_configuration()?;
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// Calculate phase offset work (POW)
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let phase_res: u64 = 1 << 16;
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let pow = ((phase_res as f64) * phase_offset / 360.0) as u16;
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let pow = self.degree_to_pow(phase_offset);
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// Read existing amplitude/frequency data
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let mut register: [u8; 8] = [0; 8];
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@ -445,12 +436,7 @@ where
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self.enable_single_tone_configuration()?;
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// Calculate amplitude_scale_factor (ASF)
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let amp_res: u64 = 1 << 14;
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let asf :u16 = if amp_scale_factor == 1.0 {
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0x3FFF
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} else {
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((amp_res as f64) * amp_scale_factor) as u16
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};
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let asf = self.amplitude_to_asf(amp_scale_factor);
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// Read existing frequency/phase data
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let mut register: [u8; 8] = [0; 8];
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@ -496,16 +482,91 @@ where
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])
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}
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/*
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* Configure a RAM mode profile, but with RAM data generated by a closure
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*/
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pub fn set_ram_profile_with_closure<F>(&mut self, profile: u8, start_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64, f: F) -> Result<(), Error<E>>
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where
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F: FnOnce() -> ArrayVec::<[f64; 2048]>
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{
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// Check the legality of the profile setup
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assert!(profile < 7);
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assert!(start_addr < 1024);
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let mut vec = f();
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if (ram_dst != RAMDestination::Polar && ((vec.len() as u16) + start_addr) < 1024) ||
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((((vec.len()/2) as u16) + start_addr) < 1024) {
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return Err(Error::DDSRAMError);
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}
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// TODO: Convert argument into bytes for RAM
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let mut byte_vec: ArrayVec<[u8; 8192]> = ArrayVec::new();
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match ram_dst {
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RAMDestination::Frequency => {
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for freq in vec.into_iter() {
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let ftw = self.frequency_to_ftw(freq);
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byte_vec.push(((ftw >> 24) & 0xFF) as u8);
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byte_vec.push(((ftw >> 16) & 0xFF) as u8);
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byte_vec.push(((ftw >> 8) & 0xFF) as u8);
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byte_vec.push(((ftw >> 0) & 0xFF) as u8);
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}
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}
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RAMDestination::Phase => {
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for deg in vec.into_iter() {
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let pow = self.degree_to_pow(deg);
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byte_vec.push(((pow >> 8) & 0xFF) as u8);
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byte_vec.push(((pow >> 0) & 0xFF) as u8);
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byte_vec.push(0);
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byte_vec.push(0);
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}
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}
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RAMDestination::Amplitude => {
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for amp in vec.into_iter() {
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let asf = self.amplitude_to_asf(amp);
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byte_vec.push(((asf >> 8) & 0xFF) as u8);
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byte_vec.push(((asf << 2) & 0xFC) as u8);
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byte_vec.push(0);
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byte_vec.push(0);
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}
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}
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RAMDestination::Polar => {
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// Alternate phase and amplitude
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let mut phase = true;
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for pol in vec.into_iter() {
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if phase {
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let pow = self.degree_to_pow(pol);
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byte_vec.push(((pow >> 8) & 0xFF) as u8);
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byte_vec.push(((pow >> 0) & 0xFF) as u8);
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phase = false;
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} else {
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let asf = self.amplitude_to_asf(pol);
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byte_vec.push(((asf >> 8) & 0xFF) as u8);
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byte_vec.push(((asf << 2) & 0xFC) as u8);
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phase = true;
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}
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}
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if phase {
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return Err(Error::DDSRAMError);
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}
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}
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}
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let data = byte_vec.as_slice();
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self.set_ram_profile(profile, start_addr, start_addr + (((data.len()/4) - 1) as u16),
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ram_dst, no_dwell_high, zero_crossing, op_mode, playback_rate, data)
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}
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/*
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* Configure a RAM mode profile
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*
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* TODO: Possibly remove redundant end_addr parameter.
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* This can be inferred by start_addr and data size.
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*/
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pub fn set_ram_profile(&mut self, profile: u8, start_addr: u16, end_addr: u16,
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ram_dst: RAMDestination, no_dwell_high: bool, zero_crossing: bool,
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op_mode: RAMOperationMode, playback_rate: f64, data: &[u8]
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) -> Result<(), Error<E>> {
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// Check the legality of this setup
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// Check the legality of the profile setup
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assert!(profile < 7);
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assert!(end_addr >= start_addr);
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assert!(end_addr < 1024);
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@ -513,8 +574,8 @@ where
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// Calculate address step rate, and check legality
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let step_rate = (self.f_sys_clk/(4.0 * playback_rate)) as u64;
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if (step_rate == 0 || step_rate > 0xFFFF) {
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return Err(Error::ParameterError);
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if step_rate == 0 || step_rate > 0xFFFF {
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return Err(Error::DDSRAMError);
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}
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// Before setting up RAM, disable RAM_ENABLE
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@ -533,7 +594,7 @@ where
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])?;
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// Temporarily disable RAM mode while accessing into RAM
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self.disable_ram_configuration();
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self.disable_ram_configuration()?;
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self.write_ram(data)?;
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// Properly configure start_addr and end_addr
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@ -541,8 +602,26 @@ where
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}
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// Helper function to write data in RAM
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// Need address range for data size check
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// Calculate ftw (frequency tuning word)
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fn frequency_to_ftw(&mut self, f_out: f64) -> u32 {
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let f_res: u64 = 1 << 32;
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((f_res as f64) * f_out / self.f_sys_clk) as u32
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}
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// Calculate pow (Phase Offset Word)
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fn degree_to_pow(&mut self, phase_offset: f64) -> u16 {
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// Calculate phase offset word (POW)
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let phase_res: u64 = 1 << 16;
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((phase_res as f64) * phase_offset / 360.0) as u16
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}
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// Calculate asf (Amplitude Scale Factor)
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fn amplitude_to_asf(&mut self, amplitude: f64) -> u16 {
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let amp_res: u64 = 0x3FFF;
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((amp_res as f64) * amplitude) as u16
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}
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// Write data in RAM
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fn write_ram(&mut self, data: &[u8]) -> Result<(), Error<E>> {
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let mut vec: ArrayVec<[u8; 8192]> = ArrayVec::new();
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vec.try_push(0x16)
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