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bitmask: add mask merging

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This commit is contained in:
occheung 2020-08-26 11:04:08 +08:00
parent 181ef5c72a
commit 5f874e81b5
3 changed files with 52 additions and 34 deletions
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6
src/bitmask_macro.rs
View File

@ -1,3 +1,5 @@
use core::mem::size_of;
/* /*
* Macro builder for bit masks * Macro builder for bit masks
* $collection: Name for the bit mask collection * $collection: Name for the bit mask collection
@ -33,7 +35,7 @@ macro_rules! construct_bitmask {
pub(crate) fn get_bitmask(self) -> $unsigned_type { pub(crate) fn get_bitmask(self) -> $unsigned_type {
let mut mask: $unsigned_type = 0; let mut mask: $unsigned_type = 0;
for bit in 0..self.get_width() { for bit in 0..self.get_width() {
mask |= (1 << (self.get_shift() + bit)); mask |= (1 << (self.get_shift() + bit) % ((size_of::<$unsigned_type>() as u8) * 8));
} }
mask mask
} }
@ -48,7 +50,7 @@ macro_rules! construct_bitmask {
} }
pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type { pub(crate) fn get_filtered_content(self, data: $unsigned_type) -> $unsigned_type {
// Filter everything then shift bits // Filter everything then shift bits
((data & self.get_bitmask()) >> self.get_shift()) ((data & self.get_bitmask()) >> (self.get_shift() % ((size_of::<$unsigned_type>() as u8) * 8)))
} }
} }
} }

11
src/config_register.rs
View File

@ -1,6 +1,7 @@
use embedded_hal::blocking::spi::Transfer; use embedded_hal::blocking::spi::Transfer;
use cortex_m_semihosting::hprintln; use cortex_m_semihosting::hprintln;
use crate::Error; use crate::Error;
use core::mem::size_of;
// Bitmasks for CFG // Bitmasks for CFG
construct_bitmask!(CFGMask; u32; construct_bitmask!(CFGMask; u32;
@ -81,7 +82,7 @@ where
} }
/* /*
* Return status * Return status using mask
*/ */
pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> { pub fn get_status(&mut self, status_type: StatusMask) -> Result<u8, Error<E>> {
match self.set_all_configurations() { match self.set_all_configurations() {
@ -89,6 +90,14 @@ where
Err(e) => Err(e), Err(e) => Err(e),
} }
} }
/*
* Return entire status register
*/
pub fn get_all_status(&mut self) -> Result<u32, Error<E>> {
return self.set_all_configurations();
}
} }
impl<SPI, E> Transfer<u8> for ConfigRegister<SPI> impl<SPI, E> Transfer<u8> for ConfigRegister<SPI>

69
src/dds.rs
View File

@ -1,8 +1,10 @@
use embedded_hal::blocking::spi::Transfer; use embedded_hal::blocking::spi::Transfer;
use cortex_m_semihosting::hprintln; use cortex_m_semihosting::hprintln;
use crate::Error; use crate::Error;
use core::mem::size_of;
construct_bitmask!(CFR1Mask; u32; construct_bitmask!(DDSCFRMask; u32;
// CFR1 bitmasks
LSB_FIRST, 0, 1, LSB_FIRST, 0, 1,
SDIO_IN_ONLY, 1, 1, SDIO_IN_ONLY, 1, 1,
EXT_POWER_DOWN_CTRL, 3, 1, EXT_POWER_DOWN_CTRL, 3, 1,
@ -23,38 +25,36 @@ construct_bitmask!(CFR1Mask; u32;
INV_SINC_FILTER_ENABLE, 22, 1, INV_SINC_FILTER_ENABLE, 22, 1,
MANUAL_OSK_EXT_CTRL, 23, 1, MANUAL_OSK_EXT_CTRL, 23, 1,
RAM_PLAYBACK_DST, 29, 2, RAM_PLAYBACK_DST, 29, 2,
RAM_ENABLE, 31, 1 RAM_ENABLE, 31, 1,
);
construct_bitmask!(CFR2Mask; u32; // CFR2 bitmasks
FM_GAIN, 0, 4, FM_GAIN, 0 +32, 4,
PARALLEL_DATA_PORT_ENABLE, 4, 1, PARALLEL_DATA_PORT_ENABLE, 4 +32, 1,
SYNC_TIM_VALIDATION_DISABLE, 5, 1, SYNC_TIM_VALIDATION_DISABLE, 5 +32, 1,
DATA_ASSEM_HOLD_LAST_VALUE, 6, 1, DATA_ASSEM_HOLD_LAST_VALUE, 6 +32, 1,
MATCHED_LATENCY_ENABLE, 7, 1, MATCHED_LATENCY_ENABLE, 7 +32, 1,
TXENABLE_INV, 9, 1, TXENABLE_INV, 9 +32, 1,
PDCLK_INV, 10, 1, PDCLK_INV, 10 +32, 1,
PDCLK_ENABLE, 11, 1, PDCLK_ENABLE, 11 +32, 1,
IO_UPDATE_RATE_CTRL, 14, 2, IO_UPDATE_RATE_CTRL, 14 +32, 2,
READ_EFFECTIVE_FTW, 16, 1, READ_EFFECTIVE_FTW, 16 +32, 1,
DIGITAL_RAMP_NO_DWELL_LOW, 17, 1, DIGITAL_RAMP_NO_DWELL_LOW, 17 +32, 1,
DIGITAL_RAMP_NO_DWELL_HIGH, 18, 1, DIGITAL_RAMP_NO_DWELL_HIGH, 18 +32, 1,
DIGITAL_RAMP_ENABLE, 19, 1, DIGITAL_RAMP_ENABLE, 19 +32, 1,
DIGITAL_RAMP_DEST, 20, 2, DIGITAL_RAMP_DEST, 20 +32, 2,
SYNC_CLK_ENABLE, 22, 1, SYNC_CLK_ENABLE, 22 +32, 1,
INT_IO_UPDATE_ACTIVE, 23, 1, INT_IO_UPDATE_ACTIVE, 23 +32, 1,
EN_AMP_SCALE_SINGLE_TONE_PRO, 24, 1 EN_AMP_SCALE_SINGLE_TONE_PRO, 24 +32, 1,
);
construct_bitmask!(CFR3Mask; u32; // CFR3 bitmasks
N, 1, 7, N, 1 +64, 7,
PLL_ENABLE, 8, 1, PLL_ENABLE, 8 +64, 1,
PFD_RESET, 10, 1, PFD_RESET, 10 +64, 1,
REFCLK_IN_DIV_RESETB, 14, 1, REFCLK_IN_DIV_RESETB, 14 +64, 1,
REFCLK_IN_DIV_BYPASS, 15, 1, REFCLK_IN_DIV_BYPASS, 15 +64, 1,
I_CP, 19, 3, I_CP, 19 +64, 3,
VCO_SEL, 24, 3, VCO_SEL, 24 +64, 3,
DRV0, 28, 2 DRV0, 28 +64, 2
); );
const WRITE_MASK :u8 = 0x00; const WRITE_MASK :u8 = 0x00;
@ -86,6 +86,13 @@ where
} }
} }
// impl<SPI, E> DDS<SPI>
// where
// SPI: Transfer<u8, Error = E>
// {
// pub fn set_configuration
// }
macro_rules! impl_register_io { macro_rules! impl_register_io {
($($reg_addr: expr, $reg_byte_size: expr),+) => { ($($reg_addr: expr, $reg_byte_size: expr),+) => {
impl<SPI, E> DDS<SPI> impl<SPI, E> DDS<SPI>