forked from M-Labs/humpback-dds
migen: fix comment
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@ -1,5 +1,4 @@
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# from humpback import HumpbackPlatform
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# Import built in I/O, Connectors & Platform template
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# Import built in I/O, Connectors & Platform template for Humpback
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from migen.build.platforms.sinara import humpback
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# Import migen platform for Lattice Products
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from migen.build.lattice import LatticePlatform
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@ -7,11 +6,16 @@ from migen.build.lattice import LatticePlatform
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from migen.build.generic_platform import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.fhdl.bitcontainer import value_bits_sign
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from migen.genlib.io import *
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from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
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from migen.genlib.io import DifferentialInput
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spi_cs = [
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("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
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]
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io_update = [
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("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
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]
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class UrukulConnector(Module):
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def __init__(self, platform):
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@ -19,6 +23,8 @@ class UrukulConnector(Module):
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eem0 = [
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platform.request("eem0", 0),
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platform.request("eem0", 1),
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# Supply EEM pin with negative polarity
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# See issue/PR: https://github.com/m-labs/migen/pull/181
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platform.request("eem0_n", 2),
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platform.request("eem0", 3),
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platform.request("eem0", 4),
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@ -36,10 +42,7 @@ class UrukulConnector(Module):
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assert len(spi_cs) == 3
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assert len(io_update) == 1
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# TODO: Assert EEM resources
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assert isinstance(eem0, list)
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# Flip positive signal as negative output, maybe only do it for FPGA outputs
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# Flip negative input to positive output
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self.miso_n = Signal()
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# Very similar setup to Diff setup for iCE40 suggested, but gave B pin instead
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@ -78,12 +81,6 @@ class UrukulConnector(Module):
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if __name__ == "__main__":
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spi_cs = [
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("spi_cs", 0, Pins("B13 B14 B15"), IOStandard("LVCMOS33"))
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]
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io_update = [
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("io_update", 0, Pins("A11"), IOStandard("LVCMOS33"))
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]
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platform = humpback.Platform()
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platform.add_extension(spi_cs)
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platform.add_extension(io_update)
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