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migen: fix lvds polarity

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This commit is contained in:
occheung 2020-08-21 11:36:16 +08:00
parent 8b66b8eb9c
commit 2d7302bdca
1 changed files with 3 additions and 1 deletions
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4
migen/fpga_config.py
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@ -32,6 +32,7 @@ class UrukulConnector(Module):
# Flip positive signal as negative output, maybe only do it for FPGA outputs # Flip positive signal as negative output, maybe only do it for FPGA outputs
# self.comb += eem.n.eq(~eem.p) # self.comb += eem.n.eq(~eem.p)
self.miso_n = Signal()
self.sdo = Signal() self.sdo = Signal()
self.specials += Instance("SB_IO", self.specials += Instance("SB_IO",
@ -39,7 +40,7 @@ class UrukulConnector(Module):
p_IO_STANDARD="SB_LVDS_INPUT", p_IO_STANDARD="SB_LVDS_INPUT",
io_PACKAGE_PIN=eem2, io_PACKAGE_PIN=eem2,
i_D_OUT_0=self.sdo, i_D_OUT_0=self.sdo,
o_D_IN_0=spi.miso o_D_IN_0=self.miso_n
) )
# self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso) # self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso)
@ -55,6 +56,7 @@ class UrukulConnector(Module):
eem1.n.eq(~spi.mosi), eem1.n.eq(~spi.mosi),
# spi.miso.eq(eem2.p), # spi.miso.eq(eem2.p),
spi.miso.eq(~self.miso_n),
eem3.p.eq(spi.cs[0]), eem3.p.eq(spi.cs[0]),
eem3.n.eq(~spi.cs[0]), eem3.n.eq(~spi.cs[0]),