forked from M-Labs/zynq-rs
640 lines
20 KiB
Rust
640 lines
20 KiB
Rust
///! Register definitions for System Level Control
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use volatile_register::{RO, RW};
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use libregister::{
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register, register_at,
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register_bit, register_bits, register_bits_typed,
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RegisterW, RegisterRW,
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};
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#[repr(u8)]
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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DdrPll = 0b11,
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}
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#[repr(u8)]
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pub enum ArmPllSource {
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ArmPll = 0b00,
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DdrPll = 0b10,
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IoPll = 0b11,
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}
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#[repr(u8)]
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pub enum DdriobInputType {
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Off = 0b00,
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/// For SSTL, HSTL
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VrefDifferential = 0b01,
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Differential = 0b10,
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Lvcmos = 0b11,
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}
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#[repr(u8)]
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pub enum DdriobDciType {
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/// DDR2/3L Addr and Clock
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Disabled = 0b00,
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/// LPDDR2
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Drive = 0b01,
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/// DDR2/3/3L Data and Diff
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Termination = 0b11,
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}
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#[repr(u8)]
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pub enum DdriobOutputEn {
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Ibuf = 0b00,
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Obuf = 0b11,
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}
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#[repr(u8)]
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pub enum DdriobVrefSel {
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/// For LPDDR2 with 1.2V IO
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Vref0_6V = 0b0001,
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/// For DDR3L with 1.35V IO
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Vref0_675V = 0b0010,
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/// For DDR3 with 1.5V IO
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Vref0_75V = 0b0100,
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/// For DDR2 with 1.8V IO
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Vref0_9V = 0b1000,
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}
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#[repr(u8)]
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pub enum LevelShifterEnable {
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DisableAll = 0x0,
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EnablePsToPl = 0xA,
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EnableAll = 0xF,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub scl: RW<u32>,
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pub slcr_lock: SlcrLock,
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pub slcr_unlock: SlcrUnlock,
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pub slcr_locksta: RO<u32>,
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reserved0: [u32; 60],
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pub arm_pll_ctrl: PllCtrl,
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pub ddr_pll_ctrl: PllCtrl,
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pub io_pll_ctrl: PllCtrl,
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pub pll_status: PllStatus,
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pub arm_pll_cfg: PllCfg,
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pub ddr_pll_cfg: PllCfg,
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pub io_pll_cfg: PllCfg,
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reserved1: [u32; 1],
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pub arm_clk_ctrl: ArmClkCtrl,
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pub ddr_clk_ctrl: DdrClkCtrl,
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pub dci_clk_ctrl: DciClkCtrl,
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pub aper_clk_ctrl: AperClkCtrl,
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pub usb0_clk_ctrl: RW<u32>,
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pub usb1_clk_ctrl: RW<u32>,
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pub gem0_rclk_ctrl: RclkCtrl,
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pub gem1_rclk_ctrl: RclkCtrl,
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pub gem0_clk_ctrl: GemClkCtrl,
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pub gem1_clk_ctrl: GemClkCtrl,
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pub smc_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: LqspiClkCtrl,
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pub sdio_clk_ctrl: RW<u32>,
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pub uart_clk_ctrl: UartClkCtrl,
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pub spi_clk_ctrl: RW<u32>,
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pub can_clk_ctrl: RW<u32>,
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pub can_mioclk_ctrl: RW<u32>,
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pub dbg_clk_ctrl: RW<u32>,
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pub pcap_clk_ctrl: RW<u32>,
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pub topsw_clk_ctrl: RW<u32>,
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pub fpga0_clk_ctrl: RW<u32>,
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pub fpga0_thr_ctrl: RW<u32>,
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pub fpga0_thr_cnt: RW<u32>,
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pub fpga0_thr_sta: RO<u32>,
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pub fpga1_clk_ctrl: RW<u32>,
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pub fpga1_thr_ctrl: RW<u32>,
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pub fpga1_thr_cnt: RW<u32>,
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pub fpga1_thr_sta: RO<u32>,
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pub fpga2_clk_ctrl: RW<u32>,
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pub fpga2_thr_ctrl: RW<u32>,
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pub fpga2_thr_cnt: RW<u32>,
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pub fpga2_thr_sta: RO<u32>,
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pub fpga3_clk_ctrl: RW<u32>,
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pub fpga3_thr_ctrl: RW<u32>,
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pub fpga3_thr_cnt: RW<u32>,
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pub fpga3_thr_sta: RO<u32>,
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reserved2: [u32; 5],
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pub clk_621_true: Clk621True,
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reserved3: [u32; 14],
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pub pss_rst_ctrl: PssRstCtrl,
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pub ddr_rst_ctrl: RW<u32>,
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pub topsw_rst_ctrl: RW<u32>,
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pub dmac_rst_ctrl: RW<u32>,
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pub usb_rst_ctrl: RW<u32>,
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pub gem_rst_ctrl: RW<u32>,
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pub sdio_rst_ctrl: RW<u32>,
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pub spi_rst_ctrl: RW<u32>,
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pub can_rst_ctrl: RW<u32>,
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pub i2c_rst_ctrl: RW<u32>,
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pub uart_rst_ctrl: UartRstCtrl,
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pub gpio_rst_ctrl: RW<u32>,
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pub lqspi_rst_ctrl: LqspiRstCtrl,
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pub smc_rst_ctrl: RW<u32>,
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pub ocm_rst_ctrl: RW<u32>,
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reserved4: [u32; 1],
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pub fpga_rst_ctrl: FpgaRstCtrl,
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pub a9_cpu_rst_ctrl: A9CpuRstCtrl,
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reserved5: [u32; 1],
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pub rs_awdt_ctrl: RW<u32>,
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reserved6: [u32; 2],
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pub reboot_status: RW<u32>,
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pub boot_mode: BootMode,
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reserved7: [u32; 40],
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pub apu_ctrl: RW<u32>,
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pub wdt_clk_sel: RW<u32>,
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reserved8: [u32; 78],
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pub tz_dma_ns: RW<u32>,
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pub tz_dma_irq_ns: RW<u32>,
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pub tz_dma_periph_ns: RW<u32>,
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reserved9: [u32; 57],
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pub pss_idcode: RW<u32>,
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reserved10: [u32; 51],
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pub ddr_urgent: RW<u32>,
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reserved11: [u32; 2],
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pub ddr_cal_start: RW<u32>,
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reserved12: [u32; 1],
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pub ddr_ref_start: RW<u32>,
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pub ddr_cmd_sta: RW<u32>,
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pub ddr_urgent_sel: RW<u32>,
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pub ddr_dfi_status: RW<u32>,
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reserved13: [u32; 55],
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pub mio_pin_00: MioPin00,
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pub mio_pin_01: MioPin01,
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pub mio_pin_02: MioPin02,
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pub mio_pin_03: MioPin03,
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pub mio_pin_04: MioPin04,
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pub mio_pin_05: MioPin05,
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pub mio_pin_06: MioPin06,
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pub mio_pin_07: MioPin07,
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pub mio_pin_08: MioPin08,
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pub mio_pin_09: MioPin09,
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pub mio_pin_10: MioPin10,
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pub mio_pin_11: MioPin11,
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pub mio_pin_12: MioPin12,
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pub mio_pin_13: MioPin13,
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pub mio_pin_14: MioPin14,
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pub mio_pin_15: MioPin15,
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pub mio_pin_16: MioPin16,
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pub mio_pin_17: MioPin17,
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pub mio_pin_18: MioPin18,
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pub mio_pin_19: MioPin19,
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pub mio_pin_20: MioPin20,
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pub mio_pin_21: MioPin21,
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pub mio_pin_22: MioPin22,
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pub mio_pin_23: MioPin23,
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pub mio_pin_24: MioPin24,
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pub mio_pin_25: MioPin25,
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pub mio_pin_26: MioPin26,
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pub mio_pin_27: MioPin27,
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pub mio_pin_28: MioPin28,
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pub mio_pin_29: MioPin29,
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pub mio_pin_30: MioPin30,
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pub mio_pin_31: MioPin31,
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pub mio_pin_32: MioPin32,
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pub mio_pin_33: MioPin33,
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pub mio_pin_34: MioPin34,
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pub mio_pin_35: MioPin35,
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pub mio_pin_36: MioPin36,
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pub mio_pin_37: MioPin37,
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pub mio_pin_38: MioPin38,
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pub mio_pin_39: MioPin39,
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pub mio_pin_40: MioPin40,
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pub mio_pin_41: MioPin41,
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pub mio_pin_42: MioPin42,
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pub mio_pin_43: MioPin43,
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pub mio_pin_44: MioPin44,
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pub mio_pin_45: MioPin45,
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pub mio_pin_46: MioPin46,
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pub mio_pin_47: MioPin47,
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pub mio_pin_48: MioPin48,
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pub mio_pin_49: MioPin49,
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pub mio_pin_50: MioPin50,
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pub mio_pin_51: MioPin51,
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pub mio_pin_52: MioPin52,
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pub mio_pin_53: MioPin53,
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reserved14: [u32; 11],
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pub mio_loopback: RW<u32>,
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reserved15: [u32; 1],
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pub mio_mst_tri0: RW<u32>,
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pub mio_mst_tri1: RW<u32>,
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reserved16: [u32; 7],
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pub sd0_wp_cd_sel: RW<u32>,
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pub sd1_wp_cd_sel: RW<u32>,
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reserved17: [u32; 50],
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pub lvl_shftr_en: LvlShftr,
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reserved18: [u32; 3],
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pub ocm_cfg: RW<u32>,
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reserved19: [u32; 123],
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pub gpiob_ctrl: GpiobCtrl,
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pub gpiob_cfg_cmos18: RW<u32>,
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pub gpiob_cfg_cmos25: RW<u32>,
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pub gpiob_cfg_cmos33: RW<u32>,
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reserved20: [u32; 1],
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pub gpiob_cfg_hstl: RW<u32>,
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pub gpiob_drvr_bias_ctrl: RW<u32>,
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reserved21: [u32; 9],
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pub ddriob_addr0: DdriobConfig,
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pub ddriob_addr1: DdriobConfig,
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pub ddriob_data0: DdriobConfig,
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pub ddriob_data1: DdriobConfig,
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pub ddriob_diff0: DdriobConfig,
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pub ddriob_diff1: DdriobConfig,
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pub ddriob_clock: DdriobConfig,
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pub ddriob_drive_slew_addr: RW<u32>,
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pub ddriob_drive_slew_data: RW<u32>,
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pub ddriob_drive_slew_diff: RW<u32>,
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pub ddriob_drive_slew_clock: RW<u32>,
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pub ddriob_ddr_ctrl: DdriobDdrCtrl,
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pub ddriob_dci_ctrl: DdriobDciCtrl,
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pub ddriob_dci_status: DdriobDciStatus,
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}
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register_at!(RegisterBlock, 0xF8000000, new);
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impl RegisterBlock {
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/// Required to modify any sclr register
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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let mut self_ = Self::new();
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self_.slcr_unlock.unlock();
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let r = f(&mut self_);
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self_.slcr_lock.lock();
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r
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}
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/// Perform a soft reset
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pub fn soft_reset(&mut self) {
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self.pss_rst_ctrl.write(
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PssRstCtrl::zeroed()
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.soft_rst(true)
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);
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}
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pub fn init_preload_fpga(&mut self) {
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// Assert FPGA top level output resets
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self.fpga_rst_ctrl.write(
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FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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// Disable level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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);
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// Enable output level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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.user_lvl_shftr_en(LevelShifterEnable::EnablePsToPl)
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);
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}
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pub fn init_postload_fpga(&mut self) {
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// Enable level shifters
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self.lvl_shftr_en.write(
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LvlShftr::zeroed()
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.user_lvl_shftr_en(LevelShifterEnable::EnableAll)
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);
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// Deassert AXI interface resets
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self.fpga_rst_ctrl.write(
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FpgaRstCtrl::zeroed()
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);
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}
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}
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register!(slcr_lock, SlcrLock, WO, u32);
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register_bits!(slcr_lock, lock_key, u16, 0, 15);
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impl SlcrLock {
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pub fn lock(&mut self) {
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self.write(
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Self::zeroed()
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.lock_key(0x767B)
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);
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}
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}
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register!(slcr_unlock, SlcrUnlock, WO, u32);
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register_bits!(slcr_unlock, unlock_key, u16, 0, 15);
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impl SlcrUnlock {
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pub fn unlock(&mut self) {
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self.write(
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Self::zeroed()
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.unlock_key(0xDF0D)
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);
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}
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}
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register!(pll_ctrl, PllCtrl, RW, u32);
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register_bits!(pll_ctrl, pll_fdiv, u16, 12, 18);
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register_bit!(pll_ctrl, pll_bypass_force, 4);
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register_bit!(pll_ctrl, pll_bypass_qual, 3);
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register_bit!(pll_ctrl, pll_pwrdwn, 1);
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register_bit!(pll_ctrl, pll_reset, 0);
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register!(pll_status, PllStatus, RO, u32);
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register_bit!(pll_status, arm_pll_lock, 0);
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register_bit!(pll_status, ddr_pll_lock, 1);
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register_bit!(pll_status, io_pll_lock, 2);
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register_bit!(pll_status, arm_pll_stable, 3);
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register_bit!(pll_status, ddr_pll_stable, 4);
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register_bit!(pll_status, io_pll_stable, 5);
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impl core::fmt::Display for pll_status::Read {
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fn fmt(&self, fmt: &mut core::fmt::Formatter) -> Result<(), core::fmt::Error> {
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write!(fmt, "ARM: {}/{} DDR: {}/{} IO: {}/{}",
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if self.arm_pll_lock() { "locked" } else { "NOT locked" },
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if self.arm_pll_stable() { "stable" } else { "UNSTABLE" },
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if self.ddr_pll_lock() { "locked" } else { "NOT locked" },
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if self.ddr_pll_stable() { "stable" } else { "UNSTABLE" },
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if self.io_pll_lock() { "locked" } else { "NOT locked" },
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if self.io_pll_stable() { "stable" } else { "UNSTABLE" },
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)
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}
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}
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register!(pll_cfg, PllCfg, RW, u32);
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register_bits!(pll_cfg, pll_res, u8, 4, 7);
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register_bits!(pll_cfg, pll_cp, u8, 8, 11);
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register_bits!(pll_cfg, lock_cnt, u16, 12, 21);
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register!(arm_clk_ctrl, ArmClkCtrl, RW, u32);
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register_bit!(arm_clk_ctrl,
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/// Clock active
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cpu_peri_clkact, 28);
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register_bit!(arm_clk_ctrl, cpu_1xclkact, 27);
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register_bit!(arm_clk_ctrl, cpu_2xclkact, 26);
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register_bit!(arm_clk_ctrl, cpu_3or2xclkact, 25);
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register_bit!(arm_clk_ctrl, cpu_6or4xclkact, 24);
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register_bits!(arm_clk_ctrl,
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/// should be divisible by 2 (see TRM: 25.2 CPU Clock)
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divisor, u8, 8, 13);
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register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 4, 5);
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register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
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register_bit!(ddr_clk_ctrl, ddr_3xclkact, 0);
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register_bit!(ddr_clk_ctrl, ddr_2xclkact, 1);
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register_bits!(ddr_clk_ctrl, ddr_3xclk_divisor, u8, 20, 25);
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register_bits!(ddr_clk_ctrl, ddr_2xclk_divisor, u8, 26, 31);
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register!(dci_clk_ctrl, DciClkCtrl, RW, u32);
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register_bit!(dci_clk_ctrl, clkact, 0);
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register_bits!(dci_clk_ctrl, divisor0, u8, 8, 13);
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register_bits!(dci_clk_ctrl, divisor1, u8, 20, 25);
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register!(clk_621_true, Clk621True, RW, u32);
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register_bit!(clk_621_true, clk_621_true, 0);
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register!(aper_clk_ctrl, AperClkCtrl, RW, u32);
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register_bit!(aper_clk_ctrl, uart1_cpu_1xclkact, 21);
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register_bit!(aper_clk_ctrl, uart0_cpu_1xclkact, 20);
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impl AperClkCtrl {
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pub fn enable_uart0(&mut self) {
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self.modify(|_, w| w.uart0_cpu_1xclkact(true));
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}
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pub fn enable_uart1(&mut self) {
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self.modify(|_, w| w.uart1_cpu_1xclkact(true));
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}
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}
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register!(rclk_ctrl, RclkCtrl, RW, u32);
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register_bit!(rclk_ctrl,
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/// Ethernet controller Rx clock control
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clkact, 0);
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register_bit!(rclk_ctrl,
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/// false: MIO, true: EMIO
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srcsel, 4);
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register!(gem_clk_ctrl, GemClkCtrl, RW, u32);
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register_bits!(gem_clk_ctrl,
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/// 2nd divisor for source clock
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divisor1, u8, 20, 25);
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register_bits!(gem_clk_ctrl,
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/// 1st divisor for source clock
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divisor, u8, 8, 13);
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register_bits_typed!(gem_clk_ctrl,
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/// Source to generate the ref clock
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srcsel, u8, PllSource, 4, 6);
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register_bit!(gem_clk_ctrl,
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/// SMC reference clock control
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clkact, 0);
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits_typed!(uart_clk_ctrl, srcsel, u8, PllSource, 4, 5);
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register_at!(UartClkCtrl, 0xF8000154, new);
|
|
impl UartClkCtrl {
|
|
pub fn enable_uart0(&mut self) {
|
|
self.modify(|_, w| {
|
|
// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
|
|
// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
|
|
// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
|
|
w.divisor(0x14)
|
|
.srcsel(PllSource::IoPll)
|
|
.clkact0(true)
|
|
})
|
|
}
|
|
|
|
pub fn enable_uart1(&mut self) {
|
|
self.modify(|_, w| {
|
|
// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
|
|
// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
|
|
// c. Enable the UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] = 1.
|
|
w.divisor(0x14)
|
|
.srcsel(PllSource::IoPll)
|
|
.clkact1(true)
|
|
})
|
|
}
|
|
}
|
|
|
|
register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
|
|
register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
|
|
register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
|
|
register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
|
|
register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
|
|
register_at!(UartRstCtrl, 0xF8000228, new);
|
|
impl UartRstCtrl {
|
|
pub fn reset_uart0(&mut self) {
|
|
self.modify(|_, w|
|
|
w.uart0_ref_rst(true)
|
|
.uart0_cpu1x_rst(true)
|
|
);
|
|
self.modify(|_, w|
|
|
w.uart0_ref_rst(false)
|
|
.uart0_cpu1x_rst(false)
|
|
);
|
|
}
|
|
|
|
pub fn reset_uart1(&mut self) {
|
|
self.modify(|_, w|
|
|
w.uart1_ref_rst(true)
|
|
.uart1_cpu1x_rst(true)
|
|
);
|
|
self.modify(|_, w|
|
|
w.uart1_ref_rst(false)
|
|
.uart1_cpu1x_rst(false)
|
|
);
|
|
}
|
|
}
|
|
|
|
register!(lqspi_clk_ctrl, LqspiClkCtrl, RW, u32);
|
|
register_bit!(lqspi_clk_ctrl, clkact, 0);
|
|
register_bits_typed!(lqspi_clk_ctrl, src_sel, u8, PllSource, 4, 5);
|
|
register_bits!(lqspi_clk_ctrl, divisor, u8, 8, 13);
|
|
|
|
register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
|
|
register_bit!(lqspi_rst_ctrl, ref_rst, 1);
|
|
register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
|
|
|
|
register!(fpga_rst_ctrl, FpgaRstCtrl, RW, u32);
|
|
register_bit!(fpga_rst_ctrl, fpga0_out_rst, 0);
|
|
register_bit!(fpga_rst_ctrl, fpga1_out_rst, 1);
|
|
register_bit!(fpga_rst_ctrl, fpga2_out_rst, 2);
|
|
register_bit!(fpga_rst_ctrl, fpga3_out_rst, 3);
|
|
|
|
register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
|
|
register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
|
|
register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);
|
|
register_bit!(a9_cpu_rst_ctrl, a9_clkstop0, 4);
|
|
register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
|
|
register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
|
|
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
#[repr(u8)]
|
|
pub enum BootModePins {
|
|
Jtag = 0b000,
|
|
Nor = 0b001,
|
|
Nand = 0b010,
|
|
QuadSpi = 0b100,
|
|
SdCard = 0b110,
|
|
}
|
|
|
|
register!(boot_mode, BootMode, RO, u32);
|
|
register_bit!(boot_mode, pll_bypass, 4);
|
|
register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 3);
|
|
|
|
register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
|
|
register_bit!(pss_rst_ctrl, soft_rst, 1);
|
|
|
|
/// Used for MioPin*.io_type
|
|
#[repr(u8)]
|
|
pub enum IoBufferType {
|
|
Lvcmos18 = 0b001,
|
|
Lvcmos25 = 0b010,
|
|
Lvcmos33 = 0b011,
|
|
Hstl = 0b100,
|
|
}
|
|
|
|
macro_rules! mio_pin_register {
|
|
($mod_name: ident, $struct_name: ident) => (
|
|
register!($mod_name, $struct_name, RW, u32);
|
|
register_bit!($mod_name, disable_rcvr, 13);
|
|
register_bit!($mod_name, pullup, 12);
|
|
register_bits_typed!($mod_name, io_type, u8, IoBufferType, 9, 11);
|
|
register_bit!($mod_name, speed, 8);
|
|
register_bits!($mod_name, l3_sel, u8, 5, 7);
|
|
register_bits!($mod_name, l2_sel, u8, 3, 4);
|
|
register_bit!($mod_name, l1_sel, 2);
|
|
register_bit!($mod_name, l0_sel, 1);
|
|
register_bit!($mod_name, tri_enable, 0);
|
|
);
|
|
}
|
|
|
|
mio_pin_register!(mio_pin_00, MioPin00);
|
|
mio_pin_register!(mio_pin_01, MioPin01);
|
|
mio_pin_register!(mio_pin_02, MioPin02);
|
|
mio_pin_register!(mio_pin_03, MioPin03);
|
|
mio_pin_register!(mio_pin_04, MioPin04);
|
|
mio_pin_register!(mio_pin_05, MioPin05);
|
|
mio_pin_register!(mio_pin_06, MioPin06);
|
|
mio_pin_register!(mio_pin_07, MioPin07);
|
|
mio_pin_register!(mio_pin_08, MioPin08);
|
|
mio_pin_register!(mio_pin_09, MioPin09);
|
|
mio_pin_register!(mio_pin_10, MioPin10);
|
|
mio_pin_register!(mio_pin_11, MioPin11);
|
|
mio_pin_register!(mio_pin_12, MioPin12);
|
|
mio_pin_register!(mio_pin_13, MioPin13);
|
|
mio_pin_register!(mio_pin_14, MioPin14);
|
|
mio_pin_register!(mio_pin_15, MioPin15);
|
|
mio_pin_register!(mio_pin_16, MioPin16);
|
|
mio_pin_register!(mio_pin_17, MioPin17);
|
|
mio_pin_register!(mio_pin_18, MioPin18);
|
|
mio_pin_register!(mio_pin_19, MioPin19);
|
|
mio_pin_register!(mio_pin_20, MioPin20);
|
|
mio_pin_register!(mio_pin_21, MioPin21);
|
|
mio_pin_register!(mio_pin_22, MioPin22);
|
|
mio_pin_register!(mio_pin_23, MioPin23);
|
|
mio_pin_register!(mio_pin_24, MioPin24);
|
|
mio_pin_register!(mio_pin_25, MioPin25);
|
|
mio_pin_register!(mio_pin_26, MioPin26);
|
|
mio_pin_register!(mio_pin_27, MioPin27);
|
|
mio_pin_register!(mio_pin_28, MioPin28);
|
|
mio_pin_register!(mio_pin_29, MioPin29);
|
|
mio_pin_register!(mio_pin_30, MioPin30);
|
|
mio_pin_register!(mio_pin_31, MioPin31);
|
|
mio_pin_register!(mio_pin_32, MioPin32);
|
|
mio_pin_register!(mio_pin_33, MioPin33);
|
|
mio_pin_register!(mio_pin_34, MioPin34);
|
|
mio_pin_register!(mio_pin_35, MioPin35);
|
|
mio_pin_register!(mio_pin_36, MioPin36);
|
|
mio_pin_register!(mio_pin_37, MioPin37);
|
|
mio_pin_register!(mio_pin_38, MioPin38);
|
|
mio_pin_register!(mio_pin_39, MioPin39);
|
|
mio_pin_register!(mio_pin_40, MioPin40);
|
|
mio_pin_register!(mio_pin_41, MioPin41);
|
|
mio_pin_register!(mio_pin_42, MioPin42);
|
|
mio_pin_register!(mio_pin_43, MioPin43);
|
|
mio_pin_register!(mio_pin_44, MioPin44);
|
|
mio_pin_register!(mio_pin_45, MioPin45);
|
|
mio_pin_register!(mio_pin_46, MioPin46);
|
|
mio_pin_register!(mio_pin_47, MioPin47);
|
|
mio_pin_register!(mio_pin_48, MioPin48);
|
|
mio_pin_register!(mio_pin_49, MioPin49);
|
|
mio_pin_register!(mio_pin_50, MioPin50);
|
|
mio_pin_register!(mio_pin_51, MioPin51);
|
|
mio_pin_register!(mio_pin_52, MioPin52);
|
|
mio_pin_register!(mio_pin_53, MioPin53);
|
|
|
|
register!(lvl_shftr, LvlShftr, RW, u32);
|
|
register_bits_typed!(lvl_shftr, user_lvl_shftr_en, u8, LevelShifterEnable, 0, 3);
|
|
|
|
register!(gpiob_ctrl, GpiobCtrl, RW, u32);
|
|
register_bit!(gpiob_ctrl, vref_en, 0);
|
|
|
|
register!(ddriob_config, DdriobConfig, RW, u32);
|
|
register_bits_typed!(ddriob_config, inp_type, u8, DdriobInputType, 1, 2);
|
|
register_bit!(ddriob_config, dci_update_b, 3);
|
|
register_bit!(ddriob_config, term_en, 4);
|
|
register_bits_typed!(ddriob_config, dci_type, u8, DdriobDciType, 5, 6);
|
|
register_bit!(ddriob_config, ibuf_disable_mode, 7);
|
|
register_bit!(ddriob_config, term_disable_mode, 8);
|
|
register_bits_typed!(ddriob_config, output_en, u8, DdriobOutputEn, 9, 10);
|
|
register_bit!(ddriob_config, pullup_en, 11);
|
|
|
|
register!(ddriob_ddr_ctrl, DdriobDdrCtrl, RW, u32);
|
|
register_bit!(ddriob_ddr_ctrl, vref_int_en, 1);
|
|
register_bits_typed!(ddriob_ddr_ctrl, vref_sel, u8, DdriobVrefSel, 1, 4);
|
|
register_bit!(ddriob_ddr_ctrl, vref_ext_en_lower, 5);
|
|
register_bit!(ddriob_ddr_ctrl, vref_ext_en_upper, 6);
|
|
register_bit!(ddriob_ddr_ctrl, refio_en, 9);
|
|
|
|
register!(ddriob_dci_ctrl, DdriobDciCtrl, RW, u32);
|
|
register_bit!(ddriob_dci_ctrl, reset, 0);
|
|
register_bit!(ddriob_dci_ctrl, enable, 0);
|
|
register_bits!(ddriob_dci_ctrl, nref_opt1, u8, 6, 7);
|
|
register_bits!(ddriob_dci_ctrl, nref_opt2, u8, 8, 10);
|
|
register_bits!(ddriob_dci_ctrl, nref_opt4, u8, 11, 13);
|
|
register_bits!(ddriob_dci_ctrl, pref_opt1, u8, 14, 15);
|
|
register_bits!(ddriob_dci_ctrl, pref_opt2, u8, 17, 19);
|
|
register_bit!(ddriob_dci_ctrl, update_control, 20);
|
|
|
|
register!(ddriob_dci_status, DdriobDciStatus, RW, u32);
|
|
register_bit!(ddriob_dci_status, done, 0);
|
|
register_bit!(ddriob_dci_status, lock, 13);
|