Commit Graph

25 Commits

Author SHA1 Message Date
9bebfb49bc begin MMU implementation 2019-06-17 03:32:10 +02:00
69b65b5f72 cortex_a9 regs: allow defining bit fields 2019-06-17 01:36:11 +02:00
1e16beb707 cortex_a9::regs: use crate::regs interface 2019-06-12 00:20:23 +02:00
81a892b618 eth: recv_next() 2019-06-10 02:44:29 +02:00
f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
2d7fed6c59 link again compiler_builtins
required for memset etc
2019-06-09 01:00:58 +02:00
d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00
fd7fd0db14 main: rm unused feature #![feature(global_asm)] 2019-05-23 16:06:41 +02:00
ea62d4fdec uart: make baudrate configurable, run at 115,200 baud 2019-05-23 15:50:53 +02:00
47ec0116a9 use uart1 with more configuration 2019-05-21 01:30:54 +02:00
c88374eab1 fix SP init 2019-05-20 01:21:22 +02:00
b754581452 eth: add regs and init 2019-05-07 19:28:33 +02:00
275f297309 uart: impl fmt::Write 2019-05-07 16:45:31 +02:00
55957eea09 regs macros 2019-05-06 23:56:53 +02:00
9b414e2408 PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00