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b8818863c4
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read clocks
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2019-08-17 03:20:04 +02:00 |
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1f9ad5ff62
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delint
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2019-08-11 00:56:54 +02:00 |
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54d0f3583d
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eth: fix io configuration
phy detection now works
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2019-06-18 23:10:35 +02:00 |
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b9ca9324f0
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eth: fix initialization
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2019-06-04 23:48:33 +02:00 |
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acf995d7da
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soft_reset: rm unreachable!
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2019-05-31 00:19:20 +02:00 |
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c0610ad66a
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slcr: init gem* rclk/clk
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2019-05-30 02:26:19 +02:00 |
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ee7ae7f7cc
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slcr: add soft_rst()
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2019-05-30 00:24:51 +02:00 |
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b3da0e4c93
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slcr: define all mio_pin regs, typed io_type
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2019-05-25 02:34:58 +02:00 |
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179c617904
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add register_bits_typed! macro
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2019-05-23 18:29:05 +02:00 |
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785e726661
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RegisterW/RegisterRW: required &mut self for safety
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2019-05-23 18:01:18 +02:00 |
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62ca26fa71
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slcr: abstract with RegisterBlock
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2019-05-23 17:52:06 +02:00 |
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43b6d3acd0
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uart: wait for reset
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2019-05-21 02:53:59 +02:00 |
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47ec0116a9
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use uart1 with more configuration
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2019-05-21 01:30:54 +02:00 |
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5d02fe5c95
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slcr: with_slcr() for unlock/lock
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2019-05-21 01:30:17 +02:00 |
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351d18c10f
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add register_at! macro
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2019-05-20 23:01:50 +02:00 |
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ca9b10dce8
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refactor regs macros for RO/WO/RW access
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2019-05-07 00:32:45 +02:00 |
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fdc6c38de6
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enable_uart0(): add srcsel
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2019-05-07 00:01:43 +02:00 |
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55957eea09
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regs macros
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2019-05-06 23:56:53 +02:00 |
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9b414e2408
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PoC: boot, uart output in qemu
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2019-05-05 14:56:23 +02:00 |
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