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2d1c8e1f4f
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zynq::flash: fix txd[123] alignment
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2019-12-14 01:07:15 +01:00 |
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e1068af948
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zynq::flash: add rdsr1()
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2019-12-12 01:02:09 +01:00 |
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3b3b5dc7c1
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zynq::flash: add support for writing 1/2/3-byte words
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2019-12-12 00:17:34 +01:00 |
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70d56d2b28
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zynq::flash: doc
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2019-12-12 00:13:02 +01:00 |
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b346ea8297
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zynq::flash: fix INST_RDCR
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2019-12-12 00:11:42 +01:00 |
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e9b80eaef9
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zynq::flash: don't send excess data, fixes, refactorings
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2019-12-10 02:50:44 +01:00 |
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0823a74164
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zynq::flash: fix rx_thres register
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2019-12-10 02:46:25 +01:00 |
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aab82f6843
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zynq::flash: enable big endian mode
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2019-12-10 02:45:05 +01:00 |
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f3676c945a
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zynq::flash: flush after instruction
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2019-12-07 02:48:55 +01:00 |
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1e465250f5
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zynq::flash: enable/disable spi for every transfer
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2019-12-07 02:11:50 +01:00 |
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e37659e4b3
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zynq::flash: refactor
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2019-12-05 01:18:52 +01:00 |
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45cc271735
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zynq::flash: fix + refactor
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2019-12-05 00:05:34 +01:00 |
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cfaa1213e2
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zynq::flash: add more initialization
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2019-12-03 02:41:49 +01:00 |
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7107244a6e
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zynq::flash: start implementing Manual mode
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2019-11-30 02:48:39 +01:00 |
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dd3ad3be67
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zynq::flash: implement stopping LinearAddressing mode
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2019-11-29 23:48:08 +01:00 |
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a8a7f11990
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zynq::flash: configure quad i/o fast read mode
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2019-11-29 23:37:54 +01:00 |
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78caca1f04
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zynq::flash: setup additional signals
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2019-11-28 03:22:26 +01:00 |
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5642feb824
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zynq::flash: add missing config bits to enable addressing mode
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2019-11-28 03:02:51 +01:00 |
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a199a5dc7d
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zynq::flash: add more setup
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2019-11-23 01:59:24 +01:00 |
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3180f1c3f7
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zynq::flash: begin driver implementation
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2019-11-21 00:14:09 +01:00 |
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8037042040
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zynq::slcr: implement boot_mode bits
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2019-11-20 21:31:54 +01:00 |
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6ffcf7d4a4
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ram: lock for concurrent use
this may be reverted if ram allocation shall be more separate.
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2019-11-20 17:25:54 +01:00 |
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4f8a76e29b
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stdio: lock for use by core1
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2019-11-20 17:00:57 +01:00 |
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ff41f4dd2d
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cortex_a9::mutex: restore and fix powersaving behaviour, doc
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2019-11-20 16:30:56 +01:00 |
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d89f594ba4
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cortex_a9::mutex: use AtomU32, remove powersaving behavior
Mutex works properly now.
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2019-11-18 02:37:59 +01:00 |
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4e4ff512d9
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add cortex_a9::mutex
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2019-11-18 02:13:54 +01:00 |
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85f29ace6b
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boot: flush cache-line
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2019-11-18 01:22:57 +01:00 |
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ef6d0ff3f1
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boot: reset core1 before start
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2019-11-18 00:38:03 +01:00 |
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0bc941d789
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main: start_core1
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2019-11-16 00:53:30 +01:00 |
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a416f48af1
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main: add empty main_core1()
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2019-11-16 00:21:57 +01:00 |
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b6596d930d
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boot: ACTLR.enable_smp()
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2019-11-16 00:12:58 +01:00 |
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49901d1b8a
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boot: prepare core1 bootup
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2019-11-15 23:59:01 +01:00 |
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Björn Stein
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4a1d0fc0c3
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zynq::mpcore: add register definitions
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2019-11-14 02:11:58 +01:00 |
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50481b3a80
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main: rm obsolete compile feature
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2019-11-13 23:33:11 +01:00 |
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b76dc4037d
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main: change IP address to 192.168.1.51/24
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2019-11-13 16:02:56 +01:00 |
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caa69fda2e
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main: refactor into boot
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2019-11-11 02:46:18 +01:00 |
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3279aab961
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main: refactor into abort, panic, ram
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2019-11-11 02:46:18 +01:00 |
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92c274348f
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zynq::eth: enable checksum offload
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2019-11-11 01:42:41 +01:00 |
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3eb7fce572
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delint
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2019-11-11 01:42:38 +01:00 |
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b1472096ba
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main: change IP address to 192.168.1.28/24
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2019-11-11 01:40:07 +01:00 |
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cb1b5776cd
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Cargo.lock: update dependencies
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2019-11-11 00:45:59 +01:00 |
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3496755406
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update rust + smoltcp
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2019-11-11 00:28:46 +01:00 |
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959bf8a245
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zynq::eth: don't check_link_change if link already established
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2019-11-11 00:08:48 +01:00 |
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4d3b2ac7e5
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zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
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2019-11-11 00:06:35 +01:00 |
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cae02947bc
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zynq::eth: remove all memory barriers
They were not the solution.
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2019-11-10 23:52:55 +01:00 |
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afd96bd887
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zynq::clocks: unlock slcr in enable_io()
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2019-11-07 00:13:50 +01:00 |
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261455877d
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zynq::ddr: fix DDR 3x/2x setup, print clocks
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2019-11-07 00:13:50 +01:00 |
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ff96bf903b
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zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
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2019-11-07 00:13:50 +01:00 |
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d2df5652d0
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Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
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2019-11-07 00:13:50 +01:00 |
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eb56dda44f
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zynq::slcr::unlocked: fix comment
|
2019-11-07 00:13:50 +01:00 |
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