8fd1306145
zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
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- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
a28a819b18
add manifests target to PHONY
2023-10-09 18:29:53 +08:00
3f414278e2
cleanup
2023-10-09 18:28:20 +08:00
e5aafad60d
force cargo to use our copy of zynq-rs
2023-10-09 18:27:58 +08:00
b9a0bcabeb
ksupport: fix build on acpki variants
2023-10-09 17:10:45 +08:00
8eb359ee42
cargo fmt
2023-10-09 11:50:47 +08:00
7263862fd8
satellite: support optional args
2023-10-09 11:42:51 +08:00
29cc0a6e28
ddma/subkernel: fix wrong destination reported
2023-10-09 11:42:51 +08:00
616c40429e
satellite: process kernel requests more often
2023-10-09 11:42:51 +08:00
3ea8147966
subkernel: send async statuses when requested
2023-10-09 11:42:51 +08:00
cb79c12284
satellite: support subkernels
2023-10-09 11:42:51 +08:00
623cc7b79e
libkernel -> ksupport
2023-10-09 11:42:51 +08:00
49205eea17
satellite gateware: add kernel rtio to cri
2023-10-09 11:36:23 +08:00
6885c618b5
move kernel-related code to separate library
2023-10-09 11:36:23 +08:00
c696fd826f
master: support optional args
2023-10-09 10:35:47 +08:00
4b3c9a3d08
rtio_mgt: remove support for async messages
2023-10-09 10:35:47 +08:00
779aea7c6a
check subkernel exceptions only when awaited
2023-10-09 10:35:03 +08:00
6785ca2c85
subkernel: port master support
2023-10-09 10:35:03 +08:00
656cbf4546
kasli_soc: use sed_lanes value from HW description
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https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
2023-10-06 15:37:56 +01:00
ecd4ca333c
rtio_clocking: inform the user if PLL is bypassed
2023-10-06 16:27:25 +08:00
ae3099dd8e
kasli_soc: support 100MHz clock
2023-10-06 16:27:25 +08:00
49810da188
runtime: wait longer for PLL lock
2023-10-05 12:17:43 +08:00
e451598a06
satman: fix dma reporting wrong destination
2023-09-22 10:29:48 +08:00
f4ceca464f
drtio: change async messages to sync
2023-09-21 14:18:25 +08:00
f3dcd53086
firmware: fix zc706 compilation warnings
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-09-11 15:21:56 +08:00
b3856e879b
refactor write_rustc_cfg_file()
2023-09-11 11:48:19 +08:00
1ccae0d442
consolidate all write..file() into config.py
2023-09-11 11:48:19 +08:00
2c19f4ac31
replace rustc_cfg[ ] & change write_rustc_cfg_file
2023-09-11 11:48:19 +08:00
85ecff2cc1
cargo: update zynq-rs
2023-09-07 19:01:36 +08:00
3a305c8cac
Revert "cargo: update dependencies"
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This reverts commit 38b0799bb0
2023-09-07 19:00:16 +08:00
38b0799bb0
cargo: update dependencies
2023-09-07 18:54:30 +08:00
615f2e3d37
remove misleading 'Actively' from docs at main.rs
2023-09-06 10:53:26 +08:00
37df7fd45b
cargo fmt
2023-08-30 16:14:35 +08:00
2ac7eedec1
firmware: fix compilation without virtual LEDs
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-08-30 15:33:44 +08:00
MorganTL
c61017fbe6
fix compiling error when cfg has has_rtio_moninj
2023-08-30 15:32:09 +08:00
MorganTL
0e6309b95e
change write_rustc_cfg_file to follow artiq repo
2023-08-30 14:56:12 +08:00
1516327c26
firmware: fix zc706 compilation error
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-08-29 11:25:28 +08:00
622d267d55
add virtual LEDs, improve IO expander setup, drive TX_DISABLE
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-08-28 16:08:10 +08:00
4ae8557018
drtio: remame drtio_transceiver to gt_drtio
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Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
2023-08-28 13:05:40 +08:00
dc08c382a2
satman: wait longer for PLL lock ( #246 )
2023-08-13 13:52:12 +08:00
ca17cd419e
Revert "kasli_soc: add SFP0..3 LED indication"
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This reverts commit 5111778363
2023-08-03 10:42:09 +08:00
5111778363
kasli_soc: add SFP0..3 LED indication
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-07-24 16:30:14 +08:00
ee438105b2
json: base -> drtio_role
2023-06-16 17:03:25 +08:00
f1ee3a7584
rustfmt
2023-05-30 12:22:46 +08:00
63594d7e3d
update configuration of IBUFDS_GTE2
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Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
5e6dca61a9
analyzer: fix overflow behavior
2023-05-29 13:53:28 +08:00
b6247f409d
analyzer: fix warnings on standalone
2023-05-29 10:03:44 +08:00
6088e6bb6f
fix cargo fmt
2023-05-24 10:00:48 +08:00
ad076dd4e9
zc706: fix satellite analyzer target
2023-05-24 09:52:16 +08:00
a27b450def
runtime: port drtio-enabled analyzer
2023-05-22 15:23:40 +08:00
c536a70890
satellite gateware: add rtio analyzer
2023-05-22 15:23:24 +08:00
259b0ba1b7
satellite: port analyzer, drtio packets
2023-05-22 15:23:23 +08:00
cbc660e740
ddma: pass "uses_ddma" flag
2023-04-18 12:36:07 +08:00
8cb6cf6094
Fix mismatched signatures for the wide interface
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Lists are passed by-reference from python code, and so should be
&CSlice<_> not CSlice<_>.
2023-04-17 09:24:30 +08:00
c6fcc4e351
Add ext0_synth0_80to125 option to the clocker config
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-04-13 12:08:25 +08:00
bf50a44f76
cargo fmt
2023-04-04 11:48:48 +08:00
64cadd90f5
fix imports
2023-04-04 11:23:11 +08:00
271a1adb04
firmware: improve RTIO map error reporting
2023-04-04 11:17:26 +08:00
b747abe83c
qc2: add 4 edge counters to the end of rtio
2023-04-03 12:25:07 +08:00
48721ca9cb
apply rustfmt policies to ddma code
2023-03-27 15:53:32 +08:00
90071f7620
Master: DDMA support
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2023-03-27 15:47:54 +08:00
908dfc780e
satman: add dma support
2023-03-23 11:04:26 +08:00
4b1ce1a6ff
satellites: add rtio_dma, connect as cri master
2023-03-21 15:54:58 +08:00
a519d24074
firmware: create and apply rustfmt policy
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Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-02-22 11:02:43 +08:00
dce37a52aa
KasliSoC satellite: fix serdes timing
2023-02-20 13:07:42 +08:00
d72a2e7d07
fix previous commit
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Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-02-17 17:49:36 +08:00
05c22792d6
satman: drive SFP TX_DISABLE
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Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-02-17 17:19:30 +08:00
dcc5cc7555
satellite: add Error LED on panic
2023-02-17 16:21:52 +08:00
46b2687d70
RTIO/SYS Clock merge
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Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2023-02-17 15:52:43 +08:00
ca6e0d13ad
Remove virtual LEDs from io_expander
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 18:14:05 +08:00
b4b7912c40
Port tx_disable-related code from Kasli
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 17:44:01 +08:00
8230a01701
Build io_expander
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 15:31:22 +08:00
4bc936f071
Copy io expander from kasli
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 14:37:55 +08:00
David Nadlinger
df4988c774
rpc: Port over size/alignment fix for structs (tuples) with tail padding
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This ports over the following commits from the main ARTIQ repo:
- 8740ec3dd52d85084237797881ea137492bfe070
- dbbe8e8ed4f852e623775b7bd3aec818cdd03376
- b9f13d48aa7e2c0652210152b971b21c3c419347
2023-01-28 16:15:28 +00:00
800c12e794
fix resolve_channel_name typing
2023-01-12 16:52:36 +08:00
d36899b485
firmware: unify RTIO error message format
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Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-01-09 16:13:42 +08:00
6b3fa98d70
add channel names to RTIO errors
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Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-01-09 12:35:56 +08:00
44ef13d1c0
Fix idle/startup_kernel typos in config
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-01-03 09:55:36 +08:00
David Nadlinger
8e0229d265
si5324: crystal_{ref -> as_ckin2} [nfc]
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This makes it clear that by itself, the flag does not
cause the input mux to be changed.
2022-12-17 01:33:50 +00:00
David Nadlinger
2ddb4d259f
Undo most of Si5324 unification ( 5c054cc901)
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This reverts most of 5c054cc901
2022-12-17 01:31:14 +00:00
David Nadlinger
5c054cc901
Unify Si5324 setup code with main ARTIQ repository [nfc]
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I chose the version from the main repository for two
reasons:
- Explicitly specifying si5324_ref_input every time would
not work for the different Kasli/… hardware versions.
- Having `crystal_ref` as a setting in the configuration
is misleading if it does not actually activate the crystal
for use as a reference (but rather does
`route_crystal_to_ckin2`).
Related m-labs/artiq commits:
- 740543d4e284245248e3ff838c46505938dcae7a
- 3c7a394eff553ab75a7ea78bdd17830366504dc6
2022-12-12 23:22:01 +00:00
db0e41af6d
update zynq-rs and some Rust deps
2022-11-30 22:49:10 +08:00
c834e4f503
enable network and mgmt during Rust panic, make RTIO PLL lock failure a panic
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Closes #198 #200
Making it a soft panic makes it more involved with a bit of code duplication - setting up mgmt requires setting up the interface and sockets. Maybe can be done a bit cleaner.
```
[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_sinara_tester
****** Sinara system tester ******
[...]
ConnectionRefusedError: [Errno 111] Connection refused
[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_coremgmt -D 192.168.1.56 log
[ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting...
[ 0.005238s] INFO(runtime): detected gateware: GenericMaster
[ 0.016152s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 0.023004s] WARN(runtime): config initialization failed: SD error: Card initialization error: No card inserted, check if the card is inserted properly.
[ 0.036730s] WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[ 0.213000s] ERROR(runtime::rtio_clocking): RTIO PLL failed to lock
[ 0.224443s] INFO(libboard_zynq::i2c): PCA9548 detected
[ 0.256197s] INFO(runtime::comms): network addresses: MAC=e8-eb-1b-13-49-8b IPv4=192.168.1.56 IPv6-LL=fe80::eaeb:1bff:fe13:498b IPv6: no configured address
[ 0.270183s] ERROR(runtime::comms): There has been an error configuring the device: RTIO PLL failed to lock. Only mgmt interface will be available.
[ 4.000095s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[ 33.148521s] INFO(runtime::mgmt): received connection
```
Reviewed-on: M-Labs/artiq-zynq#199
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2022-10-21 17:56:34 +08:00
dc862a9051
match ident message with mainline
2022-10-21 12:08:11 +08:00
19e60073de
kasli_soc: ident = variant name
2022-10-21 11:55:24 +08:00
a546d0f95b
Implement reboot for artiq_coremgmt
2022-10-07 18:31:11 +08:00
d6ae646790
update dependencies
2022-10-07 18:30:39 +08:00
f3310324d7
update dependencies
2022-08-26 17:37:27 +08:00
0812f22423
update dependencies
2022-07-20 17:34:26 +08:00
b638fce069
update SEEN_ASYNC_ERRORS in destination_survey ( #195 )
...
Co-authored-by: kk105 <kkl@m-kabs.hk>
Reviewed-on: M-Labs/artiq-zynq#195
Co-authored-by: kk105 <kkl@m-labs.hk>
Co-committed-by: kk105 <kkl@m-labs.hk>
2022-06-20 17:41:08 +08:00
9ec6a1feab
dyld/rebind: support rela generation with nac3ld
2022-06-01 21:27:38 +08:00
8e144e41de
reloc: impl ARM_PREL31 handling
2022-06-01 21:27:38 +08:00
512b6bac12
reloc: add PC-relative relocation support
2022-06-01 21:27:38 +08:00
e3ed41ff32
fix index table reference type
2022-06-01 18:35:50 +08:00
97a63ca8d0
dyld: add EXIDX entry type
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The type is just for aesthetic. The interpretation of an index table entry is not our concern.
2022-06-01 18:33:19 +08:00
f0febe0ee4
change catch type to single reference
2022-05-31 18:26:30 +08:00
7a8f96dbd9
rtio_mgt: use mutex's async_lock
2022-05-25 10:39:06 +08:00
596edb480c
cargo: update zynq-rs
2022-05-25 10:37:38 +08:00
4f457d9c24
moninj: log link down at debug level
2022-05-25 10:37:38 +08:00
24df52268e
moninj: restructure timeout
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stop logging errors if satellite is unavailable
drtio: don't even send message if link is down
2022-05-25 10:37:38 +08:00
