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artiq-zynq
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Code Pull Requests Activity
99 Commits 9 Branches 0 Tags 1.8 MiB
Commit Graph

14 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq aeefdc862d update dependencies 2020-05-09 13:48:27 +08:00
Sebastien Bourdeauducq 4464b85ab3 move build artifacts out of tree 2020-05-07 13:52:40 +08:00
Sebastien Bourdeauducq 90faeb6fa2 use new core1 startup mechanism 2020-05-06 22:16:34 +08:00
Sebastien Bourdeauducq ae2cee5f7e also work around mkbootimage potential bug with szl 2020-05-06 17:47:27 +08:00
Sebastien Bourdeauducq 27466036a7 work around boot.bin/fsbl problems 
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
 2020-05-06 17:38:01 +08:00
Sebastien Bourdeauducq 7c22b72129 add FSBL startup route 
Not working (Zynq sucks) and not debuggable (can't get UART output from FSBL even with official binaries...)
 2020-05-06 16:53:54 +08:00
Sebastien Bourdeauducq 1211a6d066 build FSBL 2020-05-06 16:02:44 +08:00
Sebastien Bourdeauducq 11d839d8a6 update cargoSha256 2020-05-04 23:02:51 +08:00
Sebastien Bourdeauducq cbd591b86b update dependencies 2020-05-03 09:59:24 +08:00
Astro 9750bb8aa8 default.nix: change <artiq-fast> syntax 2020-05-03 02:25:19 +02:00
Sebastien Bourdeauducq 11b58d801d default.nix: build SD card contents 2020-05-01 11:23:00 +08:00
Sebastien Bourdeauducq dffbab2707 default.nix: fix szl filenames 2020-05-01 10:48:23 +08:00
Sebastien Bourdeauducq 2439ba1f88 add impure incremental build process, document 2020-05-01 10:07:38 +08:00
Sebastien Bourdeauducq c28c567e72 pure Nix build system 2020-04-30 21:04:28 +08:00