forked from M-Labs/artiq-zynq
si5324: fix clock source
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a22b13cc46
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6c834899e9
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@ -121,100 +121,120 @@ fn init_drtio(timer: &mut GlobalTimer)
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#[cfg(has_si5324)]
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fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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let si5324_settings = match clk {
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let (si5324_settings, si5324_ref_input) = match clk {
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 300,
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n31 : 6,
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n32 : 6,
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bwsel : 4,
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crystal_ref: false
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}
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 300,
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n31 : 6,
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n32 : 6,
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bwsel : 4,
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crystal_ref: false
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},
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si5324::Input::Ckin1
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)
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 260,
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n31 : 52,
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n32 : 52,
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bwsel : 4,
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crystal_ref: false
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}
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 260,
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n31 : 52,
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n32 : 52,
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bwsel : 4,
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crystal_ref: false
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},
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si5324::Input::Ckin1
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)
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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}
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(
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si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_ref: false
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},
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si5324::Input::Ckin1
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)
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},
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RtioClock::Int_150 => { // 150MHz output, from crystal
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info!("using internal 150MHz RTIO clock");
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 7139,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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}
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(
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 7139,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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},
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_100 => { // 100MHz output, from crystal.
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info!("using internal 100MHz RTIO clock");
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 7139,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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}
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(
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 7139,
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n32 : 7139,
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bwsel : 3,
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crystal_ref: true
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},
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
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info!("using internal 125MHz RTIO clock");
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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}
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}
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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},
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si5324::Input::Ckin2
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)
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},
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_ => { // same setting as Int_125, but fallback to default
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warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk);
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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}
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_ref: true
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},
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si5324::Input::Ckin2
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)
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}
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};
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let si5324_ref_input = si5324::Input::Ckin2;
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si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
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}
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@ -224,7 +244,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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#[cfg(has_si5324)]
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{
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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let si5324_ext_input = si5324::Input::Ckin2;
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let si5324_ext_input = si5324::Input::Ckin1;
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match clk {
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RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
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_ => setup_si5324(i2c, timer, clk),
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