forked from M-Labs/humpback-dds
urukul: failsave for PLL timeout
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parent
adc5807ff1
commit
f1069d951d
33
src/dds.rs
33
src/dds.rs
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@ -253,7 +253,12 @@ where
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}
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}
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// Finally, try enabling PLL
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// Finally, try enabling PLL
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else {
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else {
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self.enable_pll(f_sys_clk)
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self.enable_pll(f_sys_clk)?;
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if self.f_sys_clk == self.get_sys_clk_frequency()? {
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Ok(())
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} else {
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Err(Error::WaitRetry)
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}
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}
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}
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}
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}
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@ -844,6 +849,32 @@ where
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pub fn get_f_sys_clk(&mut self) -> f64 {
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pub fn get_f_sys_clk(&mut self) -> f64 {
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self.f_sys_clk
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self.f_sys_clk
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}
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}
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// Acquire real f_sys_clk
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pub fn get_sys_clk_frequency(&mut self) -> Result<f64, Error<E>> {
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// Calculate the new system clock frequency, examine the clock tree
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let mut configuration_queries = [
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// Acquire PLL status
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(DDSCFRMask::PLL_ENABLE, 0),
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// Acquire N-divider, to adjust VCO if necessary
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(DDSCFRMask::N, 0),
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// Acquire REF_CLK divider bypass
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(DDSCFRMask::REFCLK_IN_DIV_BYPASS, 0)
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];
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self.get_configurations(&mut configuration_queries)?;
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if configuration_queries[0].1 == 1 {
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// Recalculate sys_clk
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let divider :f64 = configuration_queries[1].1.into();
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Ok(self.f_ref_clk * divider)
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}
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else if configuration_queries[2].1 == 0 {
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Ok(self.f_ref_clk / 2.0)
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}
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else {
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Ok(self.f_ref_clk)
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}
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}
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}
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}
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// Strong check for bytes passed to a register
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// Strong check for bytes passed to a register
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@ -30,6 +30,16 @@ pub enum Error<E> {
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MqttCommandError,
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MqttCommandError,
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VectorOutOfSpace,
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VectorOutOfSpace,
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StringOutOfSpace,
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StringOutOfSpace,
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WaitRetry, // Prompt driver to just wait and retry
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}
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impl<E> Error<E> {
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pub fn is_wait_retry(&self) -> bool {
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match self {
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Error::WaitRetry => true,
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_ => false,
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}
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}
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}
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}
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#[derive(Debug, Clone, Serialize, Deserialize)]
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#[derive(Debug, Clone, Serialize, Deserialize)]
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@ -330,16 +340,39 @@ where
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}
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}
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pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ())
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loop {
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if let Err(e) = self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ()) {
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if e.is_wait_retry() {
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cortex_m::asm::delay(400_000);
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} else {
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return Err(e);
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}
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} else {
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break;
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}
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}
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Ok(())
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}
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}
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pub fn get_channel_sys_clk(&mut self, channel: u8) -> Result<f64, Error<E>> {
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pub fn get_channel_sys_clk(&mut self, channel: u8) -> Result<f64, Error<E>> {
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Ok(self.dds[usize::from(channel)].get_f_sys_clk())
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Ok(self.dds[usize::from(channel)].get_f_sys_clk())
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}
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}
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pub fn get_channel_calculated_sys_clk(&mut self, channel: u8) -> Result<f64, Error<E>> {
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self.dds[usize::from(channel)].get_sys_clk_frequency()
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}
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pub fn borrow_dds(&mut self, channel: u8) -> &mut DDS<SPI> {
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&mut self.dds[usize::from(channel)]
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}
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pub fn borrow_config_register(&mut self) -> &mut ConfigRegister<SPI> {
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&mut self.config_register
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}
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// Multi-dds channel functions
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// Multi-dds channel functions
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// Do not allow reading of DDS registers
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// Do not allow reading of DDS registers
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// Make sure only 1 SPI transaction is compelted per function call
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// Make sure only 1 SPI transaction is completed per function call
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// Setup NU_MASK in configuration register
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// Setup NU_MASK in configuration register
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// This selects the DDS channels that will be covered by multi_channel DDS (spi3)
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// This selects the DDS channels that will be covered by multi_channel DDS (spi3)
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