forked from M-Labs/humpback-dds
itm: enable itm logging
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ecdb114679
commit
eaaee84fbc
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@ -30,6 +30,7 @@ use cortex_m_rt::{
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// use cortex_m_semihosting::hprintln;
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// use cortex_m_semihosting::hprintln;
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// use panic_halt as _;
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// use panic_halt as _;
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use panic_itm as _;
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use rtic::cyccnt::{Instant, U32Ext};
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use rtic::cyccnt::{Instant, U32Ext};
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@ -83,14 +84,20 @@ fn main() -> ! {
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let ccdr = rcc
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let ccdr = rcc
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.use_hse(8.mhz())
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.use_hse(8.mhz())
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.sysclk(400.mhz())
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.sysclk(400.mhz())
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// .hclk(200.mhz())
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.hclk(200.mhz())
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// .per_ck(100.mhz())
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.per_ck(100.mhz())
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.pll1_q_ck(48.mhz()) // for SPI
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.pll1_q_ck(48.mhz()) // for SPI
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// .pll1_r_ck(400.mhz()) // for TRACECK
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.pll1_r_ck(400.mhz()) // for TRACECK
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// .pll2_p_ck(100.mhz())
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.pll2_p_ck(100.mhz())
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// .pll2_q_ck(100.mhz())
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.pll2_q_ck(100.mhz())
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.freeze(vos, &dp.SYSCFG);
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.freeze(vos, &dp.SYSCFG);
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// info!("{}", ccdr.clocks.c_ck().0);
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unsafe {
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logger::enable_itm(&dp.DBGMCU, &mut cp.DCB, &mut cp.ITM);
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}
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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@ -108,6 +115,10 @@ fn main() -> ! {
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let mut green_led = gpiob.pb0.into_push_pull_output();
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let mut green_led = gpiob.pb0.into_push_pull_output();
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green_led.set_low().unwrap();
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green_led.set_low().unwrap();
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gpiob.pb3.into_alternate_af0().set_speed(Speed::VeryHigh);
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logger::init();
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// Configure ethernet IO
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// Configure ethernet IO
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{
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{
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let _rmii_refclk = gpioa.pa1.into_alternate_af11().set_speed(Speed::VeryHigh);
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let _rmii_refclk = gpioa.pa1.into_alternate_af11().set_speed(Speed::VeryHigh);
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@ -254,9 +265,10 @@ fn main() -> ! {
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}
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}
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match net_interface.poll_delay(&sockets, clock.elapsed()) {
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match net_interface.poll_delay(&sockets, clock.elapsed()) {
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Some(net::time::Duration {millis :0}) => debug!("resuming"),
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Some(net::time::Duration {millis :0}) => {
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continue;
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}
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Some(time_delay) => {
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Some(time_delay) => {
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info!("sleeping for {} ms", time_delay);
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// green_led.set_low().unwrap();
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// green_led.set_low().unwrap();
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// delay.delay_ms(time_delay.total_millis() as u32);
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// delay.delay_ms(time_delay.total_millis() as u32);
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// green_led.set_high().unwrap();
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// green_led.set_high().unwrap();
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@ -26,7 +26,7 @@ pub unsafe fn enable_itm(
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*(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55;
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*(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55;
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// SWO CODR Register: Set SWO speed
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// SWO CODR Register: Set SWO speed
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*(0x5c00_3010 as *mut _) = 400 - 1;
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*(0x5c00_3010 as *mut _) = 200;
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// SWO SPPR Register:
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// SWO SPPR Register:
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// 1 = Manchester
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// 1 = Manchester
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@ -64,7 +64,7 @@ use cortex_m_log::{
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lazy_static! {
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lazy_static! {
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static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
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static ref LOGGER: Logger<ItmSync<InterruptFree>> = Logger {
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level: LevelFilter::Debug,
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level: LevelFilter::Trace,
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inner: unsafe {
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inner: unsafe {
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InterruptSync::new(
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InterruptSync::new(
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ItmDest::new(cortex_m::Peripherals::steal().ITM)
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ItmDest::new(cortex_m::Peripherals::steal().ITM)
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@ -77,7 +77,7 @@ pub fn init() {
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cortex_m_log::log::init(&LOGGER).unwrap();
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cortex_m_log::log::init(&LOGGER).unwrap();
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}
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}
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use panic_semihosting as _;
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// use panic_semihosting as _;
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use cortex_m_log::printer::semihosting;
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use cortex_m_log::printer::semihosting;
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use cortex_m_log::printer::semihosting::Semihosting;
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use cortex_m_log::printer::semihosting::Semihosting;
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@ -12,7 +12,9 @@ break HardFault
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break rust_begin_unwind
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break rust_begin_unwind
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# print using semihosting, slow af
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# print using semihosting, slow af
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monitor arm semihosting enable
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# monitor arm semihosting enable
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monitor tpiu config internal itm.fifo uart off 400000000
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monitor itm port 0 on
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# flash the program to STM32
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# flash the program to STM32
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load
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load
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@ -12,9 +12,9 @@ break HardFault
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break rust_begin_unwind
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break rust_begin_unwind
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# print using semihosting, slow af
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# print using semihosting, slow af
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monitor arm semihosting enable
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# monitor arm semihosting enable
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# monitor tpiu config internal itm.fifo uart off 400000000
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monitor tpiu config internal itm.fifo uart off 400000000
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# monitor itm port 0 on
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monitor itm port 0 on
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# flash the program to STM32
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# flash the program to STM32
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load
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load
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