forked from M-Labs/humpback-dds
fpga config: included into lib
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89f9b48073
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@ -17,6 +17,8 @@ use cortex_m_rt::entry;
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use core::ptr;
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use nb::block;
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use firmware::flash::flash_ice40_fpga;
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#[path = "util/logger.rs"]
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mod logger;
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@ -74,65 +76,10 @@ fn main() -> ! {
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&ccdr.clocks,
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);
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// Data buffer setup
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let mut dummy_byte :[u8; 1] = [0x00];
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let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
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// Drive CRESET_B low
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fpga_creset.set_low().unwrap();
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// Drive SPI_SS_B low
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fpga_ss.set_low().unwrap();
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// Wait at least 200ns
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delay.delay_us(1_u16);
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// Drive CRESET_B high
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fpga_creset.set_high().unwrap();
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// Wait at least another 1200us to clear internal config memory
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delay.delay_us(1200_u16);
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// Before data transmission starts, check if C_DONE is truly dine
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match fpga_cdone.is_high() {
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Ok(false) => debug!("Reset successful!"),
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Ok(_) => debug!("Reset unsuccessful!"),
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Err(_) => debug!("Reset error!"),
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};
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// Set SPI_SS_B high
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fpga_ss.set_high().unwrap();
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// Send 8 dummy clock, effectively 1 byte of 0x00
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fpga_cfg_spi.transfer(&mut dummy_byte).unwrap();
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// Drive SPI_SS_B low
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fpga_ss.set_low().unwrap();
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// Send the whole image without interruption
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// Pre-load the configuration bytes
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let config_data = include_bytes!("../build/top.bin");
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for byte in config_data.into_iter() {
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block!(fpga_cfg_spi.send(*byte)).unwrap();
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block!(fpga_cfg_spi.read()).unwrap();
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}
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// Drive SPI_SS_B high
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fpga_ss.set_high().unwrap();
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// Send at another 100 dummy clocks (choosing 13 bytes)
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fpga_cfg_spi.transfer(&mut dummy_13_bytes).unwrap();
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// Check the CDONE output from FPGA
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if !(fpga_cdone.is_high().unwrap()) {
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debug!("ERROR!");
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}
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else {
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debug!("Configuration successful!");
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// Send at least another 49 clock cycles to activate IO pins (choosing same 13 bytes)
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fpga_cfg_spi.transfer(&mut dummy_13_bytes).unwrap();
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debug!("User I/O pins activated.");
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}
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flash_ice40_fpga(fpga_cfg_spi, fpga_ss, fpga_creset, fpga_cdone, delay, config_data)?;
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loop {
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nop();
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@ -0,0 +1,99 @@
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use embedded_hal::{
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digital::v2::{OutputPin, InputPin},
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blocking::spi::Transfer,
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blocking::delay::{DelayMs, DelayUs},
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};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_rt::entry;
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use core::ptr;
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use nb::block;
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use log::{warn, debug};
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pub enum FPGAFlashError {
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SPICommunicationError,
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NegotiationError,
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ResetStatusError,
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}
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// A public method to flash iCE40 FPGA on Humpback
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pub fn flash_ice40_fpga<SPI: Transfer<u8>,
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SS: OutputPin,
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RST: OutputPin,
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DELAY: DelayUs<u32>,
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DONE: InputPin>
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(mut spi: SPI, mut ss: SS, mut creset: RST, cdone: DONE, mut delay: DELAY, data: &[u8]) -> Result<(), FPGAFlashError>
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{
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// Data buffer setup
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let mut dummy_byte :[u8; 1] = [0x00];
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let mut dummy_13_bytes :[u8; 13] = [0x00; 13];
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// Drive CRESET_B low
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creset.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Drive SPI_SS_B low
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ss.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Wait at least 200ns
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delay.delay_us(1_u32);
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// Drive CRESET_B high
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creset.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Wait at least another 1200us to clear internal config memory
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delay.delay_us(1200_u32);
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// Before data transmission starts, check if C_DONE is truly low
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// If C_DONE is high, the FPGA reset procedure is unsuccessful
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match cdone.is_low() {
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Ok(true) => {},
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_ => return Err(FPGAFlashError::ResetStatusError),
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};
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// Set SPI_SS_B high
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ss.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send 8 dummy clock, effectively 1 byte of 0x00
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spi.transfer(&mut dummy_byte)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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// Drive SPI_SS_B low
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ss.set_low()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send the whole image without interruption
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for byte in data.into_iter() {
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let mut single_byte_slice = [*byte];
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spi.transfer(&mut single_byte_slice)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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}
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// Drive SPI_SS_B high
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ss.set_high()
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.map_err(|_| FPGAFlashError::NegotiationError)?;
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// Send at another 100 dummy clocks (choosing 13 bytes)
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spi.transfer(&mut dummy_13_bytes)
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.map_err(|_| FPGAFlashError::SPICommunicationError)?;
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// Check the CDONE output from FPGA
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// CDONE needs to be high
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match cdone.is_high() {
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Ok(true) => {},
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_ => return Err(FPGAFlashError::ResetStatusError),
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};
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debug!("Configuration successful!");
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// Send at least another 49 clock cycles to activate IO pins (choosing same 13 bytes)
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spi.transfer(&mut dummy_13_bytes).map_err(|_| FPGAFlashError::SPICommunicationError)?;
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debug!("User I/O pins activated.");
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Ok(())
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}
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