forked from M-Labs/humpback-dds
cfg_reg: reorganize bitmasks
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@ -1,29 +1,6 @@
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use embedded_hal::blocking::spi::Transfer;
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use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use crate::Error;
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/*
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* Bit Masks for CFG_Write
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*/
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const RF_SW :u32 = 0x0000000F;
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const LED :u32 = 0x000000F0;
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const PROFILE :u32 = 0x00000700;
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const IO_UPDATE :u32 = 0x00001000;
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const MASK_NU :u32 = 0x0001E000;
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const CLK_SEL0 :u32 = 0x00020000;
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const SYNC_SEL :u32 = 0x00040000;
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const RST :u32 = 0x00080000;
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const IO_RST :u32 = 0x00100000;
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const CLK_SEL1 :u32 = 0x00200000;
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const DIV :u32 = 0x00C00000;
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/*
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* Bit Masks for CFG_Read
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*/
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const SMP_ERR :u32 = 0x000000F0;
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const PLL_LOCK :u32 = 0x00000F00;
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const IFC_MODE :u32 = 0x0000F000;
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const PROTO_DEV :u32 = 0x007F0000;
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/*
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/*
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* Macro builder for bit masks
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* Macro builder for bit masks
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*/
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*/
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@ -68,7 +45,8 @@ macro_rules! construct_bitmask {
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}
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}
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construct_bitmask!(CFGMask;
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construct_bitmask!(CFGMask;
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RF_SW, 0, 4,
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// Bitmasks for CFG write
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RF_SW, 0, 4, // Reuse RF_SW for Status register
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LED, 4, 4,
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LED, 4, 4,
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PROFILE, 8, 3,
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PROFILE, 8, 3,
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IO_UPDATE, 12, 1,
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IO_UPDATE, 12, 1,
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@ -78,7 +56,12 @@ construct_bitmask!(CFGMask;
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RST, 19, 1,
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RST, 19, 1,
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IO_RST, 20, 1,
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IO_RST, 20, 1,
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CLK_SEL1, 21, 1,
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CLK_SEL1, 21, 1,
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DIV, 22, 2
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DIV, 22, 2,
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// BitMasks for CFG read
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SMP_ERR, 4, 4,
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PLL_LOCK, 8, 4,
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IFC_MODE, 12, 4,
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PROTO_KEY, 16, 7
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);
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);
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pub struct ConfigRegister<SPI> {
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pub struct ConfigRegister<SPI> {
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