forked from M-Labs/humpback-dds
dds: more clk ctrl; scpi: sys_clk ctrl
This commit is contained in:
parent
331d1ff86f
commit
e1abf87351
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@ -18,7 +18,7 @@ libm = "0.2.0"
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embedded-nal = "0.1.0"
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minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
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heapless = "0.5.5"
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arrayvec = { version = "0.5.1", default-features = false, features = ["array-sizes-33-128", "array-sizes-129-255"] }
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arrayvec = { version = "0.5.1", default-features = false, features = [ "array-sizes-33-128", "array-sizes-129-255" ] }
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# Logging and Panicking
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panic-itm = "0.4.1"
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@ -31,7 +31,7 @@ lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
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git = "https://github.com/occheung/scpi-rs"
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branch = "issue-4"
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default-features = false
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features = [ "build-info", "unit-frequency" ]
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features = [ "build-info", "unit-frequency", "unit-angle" ]
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# Use below SCPI dependency when need to modify SCPI fork offline
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# [dependencies.scpi]
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@ -47,13 +47,15 @@ use firmware::{
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Channel1SwitchCommand,
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Channel2SwitchCommand,
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Channel3SwitchCommand,
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Channel0SystemClockCommand,
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Channel0AttenuationCommand,
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Channel1AttenuationCommand,
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Channel2AttenuationCommand,
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Channel3AttenuationCommand,
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ClockSourceCommand,
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ClockDivisionCommand,
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ProfileCommand
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ProfileCommand,
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Channel0Profile0Singletone
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},
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Urukul, scpi_root, recursive_scpi_tree, scpi_tree
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};
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@ -208,8 +210,7 @@ fn main() -> ! {
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let switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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let mut urukul = Urukul::new(
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
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[25_000_000.0, 25_000_000.0, 25_000_000.0, 25_000_000.0]
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7
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);
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// Setup ethernet pins
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@ -44,6 +44,7 @@ use firmware::{
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ClockSourceCommand,
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ClockDivisionCommand,
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ProfileCommand,
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Channel0Profile0Singletone
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},
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Urukul, scpi_root, recursive_scpi_tree, scpi_tree
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};
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@ -209,8 +210,7 @@ fn main() -> ! {
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let parts = cpld.split();
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let mut urukul = Urukul::new(
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
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[25_000_000.0, 25_000_000.0, 25_000_000.0, 25_000_000.0]
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7
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);
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cp.SCB.invalidate_icache();
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20
src/dds.rs
20
src/dds.rs
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@ -216,6 +216,22 @@ where
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}
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}
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// Change sys_clk frequency, method to be determined
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pub fn set_sys_clk_frequency(&mut self, f_sys_clk: f64) -> Result<(), Error<E>> {
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// If f_sys_clk is exactly the same as f_ref_clk, then invoke enable_normal_ref_clk
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if f_sys_clk == self.f_ref_clk {
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self.enable_normal_ref_clk()
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}
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// Otherwise, if the requested sys_clk is half of ref_clk, invoke enable_divided_ref_clk
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else if f_sys_clk == (self.f_ref_clk / 2.0) {
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self.enable_divided_ref_clk()
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}
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// Finally, try enabling PLL
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else {
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self.enable_pll(f_sys_clk)
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}
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}
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#[allow(non_snake_case)]
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fn get_VCO_no(&mut self, f_sys_clk: f64, divider: u8) -> Result<u8, Error<E>> {
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// Select a VCO
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@ -310,8 +326,8 @@ where
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/*
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* Set a single tone profile
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* Phase: Expressed in positive degree
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* Frequency: Must be integer
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* Phase: Expressed in positive degree, i.e. [0.0, 360.0)
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* Frequency: Must be non-negative
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* Amplitude: In a scale from 0 to 1, taking float
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*/
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pub fn set_single_tone_profile(&mut self, profile: u8, f_out: f64, phase_offset: f64, amp_scale_factor: f64) -> Result<(), Error<E>> {
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50
src/lib.rs
50
src/lib.rs
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@ -72,6 +72,7 @@ pub struct Urukul<SPI> {
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config_register: ConfigRegister<SPI>,
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attenuator: Attenuator<SPI>,
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dds: [DDS<SPI>; 4],
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f_master_clk: f64,
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}
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impl<SPI, E> Urukul<SPI>
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@ -82,17 +83,21 @@ where
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* Master constructor for the entire Urukul device
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* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
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*/
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [f64; 4]) -> Self {
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI) -> Self {
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// Construct Urukul
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Urukul {
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config_register: ConfigRegister::new(spi1),
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attenuator: Attenuator::new(spi2),
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// Create 4 DDS instances with fixed 25MHz clock
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// Counter-intuitive to assign urukul clock before having a urukul
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dds: [
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DDS::new(spi4, f_ref_clks[1]),
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DDS::new(spi5, f_ref_clks[1]),
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DDS::new(spi6, f_ref_clks[2]),
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DDS::new(spi7, f_ref_clks[3]),
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DDS::new(spi4, 25_000_000.0),
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DDS::new(spi5, 25_000_000.0),
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DDS::new(spi6, 25_000_000.0),
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DDS::new(spi7, 25_000_000.0),
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],
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// Default clock selection: OSC, fixed 100MHz speed
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f_master_clk: 100_000_000.0,
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}
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}
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@ -128,10 +133,11 @@ where
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for chip_no in 0..4 {
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self.dds[chip_no].init()?;
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}
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// Clock tree reset. CPLD divides clock frequency by 4 by default.
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// Clock tree reset. OSC clock source by default
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self.f_master_clk = 100_000_000.0;
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// CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(25_000_000.0)?;
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self.dds[chip_no].set_ref_clk_frequency(self.f_master_clk / 4.0)?;
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}
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Ok(())
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}
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@ -158,6 +164,8 @@ pub trait UrukulTraits {
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fn set_clock_division(&mut self, division: u8) -> Result<(), Self::Error>;
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Self::Error>;
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fn set_profile(&mut self, profile: u8) -> Result<(), Self::Error>;
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fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Self::Error>;
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fn set_channel_sys_clk(&mut self, channel: u8, sys_clk: f64) -> Result<(), Self::Error>;
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}
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impl<SPI, E> UrukulTraits for Urukul<SPI>
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@ -207,13 +215,16 @@ where
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(CFGMask::CLK_SEL0, 1),
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]),
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}?;
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// Save the new master clock frequency
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self.f_master_clk = frequency;
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// Calculate reference clock frequency after clock division from configuration register
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let frequency = frequency / (self.config_register.get_configuration(CFGMask::DIV) as f64);
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let f_ref_clk = self.f_master_clk / (self.config_register.get_configuration(CFGMask::DIV) as f64);
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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self.dds[dds_channel].set_ref_clk_frequency(frequency)?;
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self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
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}
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Ok(())
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}
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@ -230,7 +241,16 @@ where
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(CFGMask::DIV, 3),
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]),
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_ => Err(Error::ParameterError),
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}.map(|_| ())
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}?;
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// Calculate reference clock frequency after clock division from configuration register
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let f_ref_clk = self.f_master_clk / (division as f64);
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
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}
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Ok(())
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}
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Self::Error> {
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@ -242,4 +262,12 @@ where
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(CFGMask::PROFILE, profile.into())
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]).map(|_| ())
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}
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fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Self::Error> {
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self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
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}
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fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Self::Error> {
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self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk)
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}
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}
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106
src/main.rs
106
src/main.rs
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@ -112,7 +112,7 @@ fn main() -> ! {
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let mut config = ConfigRegister::new(parts.spi1);
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let mut att = Attenuator::new(parts.spi2);
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let mut dds0 = DDS::new(parts.spi4, 25_000_000);
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let mut dds0 = DDS::new(parts.spi4, 25_000_000.0);
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// Reset all DDS, set CLK_SEL to 0
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config.set_configurations(&mut [
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@ -135,75 +135,75 @@ fn main() -> ! {
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(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
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]).unwrap();
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dds0.enable_pll(1_000_000_000).unwrap();
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dds0.set_sys_clk_frequency(1_000_000_000.0).unwrap();
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// Attenuator
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att.set_attenuation([
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0.0, 31.5, 24.0, 0.0
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5.0, 31.5, 24.0, 0.0
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]).unwrap();
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dds0.set_single_tone_profile(1, 10_000_000, 0.0, 0.5).unwrap();
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dds0.set_single_tone_profile(1, 10_000_000.0, 0.0, 0.5).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 1),
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]).unwrap();
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// Setup RAM configuration
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 1),
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(DDSCFRMask::RAM_PLAYBACK_DST, 2),
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]).unwrap();
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// // Setup RAM configuration
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// dds0.set_configurations(&mut [
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// (DDSCFRMask::RAM_ENABLE, 1),
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// (DDSCFRMask::RAM_PLAYBACK_DST, 2),
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// ]).unwrap();
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// Configure RAM profile 0
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dds0.write_register(0x0E, &mut [
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0x00, // Open
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0x09, 0xC4, // Address step rate (2500)
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0xFF, 0xC0, // End at address 1023
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0x00, 0x00, // Start at address 0
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0x04, // Recirculate mode
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]).unwrap();
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// // Configure RAM profile 0
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// dds0.write_register(0x0E, &mut [
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// 0x00, // Open
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// 0x09, 0xC4, // Address step rate (2500)
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// 0xFF, 0xC0, // End at address 1023
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// 0x00, 0x00, // Start at address 0
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// 0x04, // Recirculate mode
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// ]).unwrap();
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debug!("{:#X?}", dds0.read_register(0x0E, &mut[
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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]).unwrap());
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// debug!("{:#X?}", dds0.read_register(0x0E, &mut[
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// 0x00, 0x00, 0x00, 0x00,
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// 0x00, 0x00, 0x00, 0x00,
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// ]).unwrap());
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// Choose profile 0
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 0),
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]).unwrap();
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// // Choose profile 0
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// config.set_configurations(&mut [
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// (CFGMask::PROFILE, 0),
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// ]).unwrap();
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// Set RAM to be amplitudes, disable RAM momentarily
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_PLAYBACK_DST, 0),
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(DDSCFRMask::RAM_ENABLE, 0),
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]).unwrap();
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// // Set RAM to be amplitudes, disable RAM momentarily
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// dds0.set_configurations(&mut [
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// (DDSCFRMask::RAM_PLAYBACK_DST, 0),
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// (DDSCFRMask::RAM_ENABLE, 0),
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// ]).unwrap();
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let mut ram_data: [u8; ((1024 * 4) + 1)] = [0; (1024 * 4) + 1];
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ram_data[0] = 0x16;
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for index in 0..1024 {
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if index % 2 == 1 {
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ram_data[(index * 4) + 1] = 0x3F;
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ram_data[(index * 4) + 2] = 0xFF;
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} else {
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ram_data[(index * 4) + 1] = 0x00;
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ram_data[(index * 4) + 2] = 0x00;
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}
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// ram_data[(index * 4) + 1] = ((index >> 2) & 0xFF) as u8;
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// ram_data[(index * 4) + 2] = ((index & 0x03) << 6) as u8;
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}
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dds0.transfer(&mut ram_data).unwrap();
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// let mut ram_data: [u8; ((1024 * 4) + 1)] = [0; (1024 * 4) + 1];
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// ram_data[0] = 0x16;
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// for index in 0..1024 {
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// if index % 2 == 1 {
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// ram_data[(index * 4) + 1] = 0x3F;
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// ram_data[(index * 4) + 2] = 0xFF;
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// } else {
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// ram_data[(index * 4) + 1] = 0x00;
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// ram_data[(index * 4) + 2] = 0x00;
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// }
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// // ram_data[(index * 4) + 1] = ((index >> 2) & 0xFF) as u8;
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// // ram_data[(index * 4) + 2] = ((index & 0x03) << 6) as u8;
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// }
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// dds0.transfer(&mut ram_data).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 1),
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]).unwrap();
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// config.set_configurations(&mut [
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// (CFGMask::PROFILE, 1),
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// ]).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 0),
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]).unwrap();
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// config.set_configurations(&mut [
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// (CFGMask::PROFILE, 0),
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// ]).unwrap();
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 1),
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]).unwrap();
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// dds0.set_configurations(&mut [
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// (DDSCFRMask::RAM_ENABLE, 1),
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// ]).unwrap();
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loop {}
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}
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87
src/scpi.rs
87
src/scpi.rs
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@ -13,6 +13,7 @@ use scpi::{
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};
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use scpi::suffix::{Amplitude, Db};
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use uom::si::frequency::{gigahertz, hertz, kilohertz, megahertz, Frequency};
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use uom::si::angle::{degree, gon, minute as aminute, radian, revolution, Angle};
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use uom::si::{f32, f64};
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use embedded_hal::blocking::spi::Transfer;
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@ -116,7 +117,11 @@ macro_rules! scpi_tree {
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scpi_root!(
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"CHANNEL0" => {
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"SWitch" => Channel0SwitchCommand,
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"Attenuation" => Channel0AttenuationCommand
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"Attenuation" => Channel0AttenuationCommand,
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"SYSCLOCK" => Channel0SystemClockCommand,
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"PROFILE0" => {
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"SINGLEtone" => Channel0Profile0Singletone
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}
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},
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"CHANNEL1" => {
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"SWitch" => Channel1SwitchCommand,
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@ -164,11 +169,16 @@ pub struct Channel2SwitchCommand {}
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pub struct Channel3SwitchCommand {}
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pub struct ClockSourceCommand {}
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pub struct ClockDivisionCommand {}
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pub struct Channel0SystemClockCommand {}
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pub struct Channel0AttenuationCommand {}
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pub struct Channel1AttenuationCommand {}
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pub struct Channel2AttenuationCommand {}
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pub struct Channel3AttenuationCommand {}
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pub struct ProfileCommand {}
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pub struct Channel0Profile0Singletone {}
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pub struct Channel0Profile0SingletoneFrequency {}
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pub struct Channel0Profile0SingletonePhase {}
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pub struct Channel0Profile0SingletoneAmplitude {}
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impl<T: Device + UrukulTraits> Command<T> for Channel0SwitchCommand {
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nquery!();
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|
@ -253,7 +263,7 @@ impl<T:Device + UrukulTraits> Command<T> for ClockSourceCommand {
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_ => Err(ErrorCode::IllegalParameterValue.into()),
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})
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})?;
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trace!("Received frequency: {:?}", frequency);
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trace!("Received master clock frequency: {:?}", frequency);
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let clock_source = match s_str {
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source if source.eq_ignore_ascii_case("OSC") => {
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|
@ -302,6 +312,28 @@ impl<T:Device + UrukulTraits> Command<T> for ClockDivisionCommand {
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}
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}
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impl<T:Device + UrukulTraits> Command<T> for Channel0SystemClockCommand {
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nquery!();
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||||
|
||||
// Param: <frequency>
|
||||
// The exact method of generating this frequency is auto-decided
|
||||
// The process is delegated to individual DDS chip
|
||||
fn event(&self, context: &mut Context<T>, args: &mut Tokenizer) -> Result<()> {
|
||||
|
||||
let frequency: f64::Frequency = args.next_data(true)?
|
||||
.map_or(Ok(f64::Frequency::new::<hertz>(0.0)), |t| {
|
||||
t.numeric(|s| match s {
|
||||
NumericValues::Default => Ok(f64::Frequency::new::<hertz>(0.0)),
|
||||
_ => Err(ErrorCode::IllegalParameterValue.into()),
|
||||
})
|
||||
})?;
|
||||
trace!("Received channel 0 system clock frequency: {:?}", frequency);
|
||||
|
||||
// Setup sys_clk through urukul interface
|
||||
context.device.set_channel_sys_clk(0, frequency.get::<hertz>()).map_err(|_| Error::new(ErrorCode::IllegalParameterValue))
|
||||
}
|
||||
}
|
||||
|
||||
impl<T:Device + UrukulTraits> Command<T> for Channel0AttenuationCommand {
|
||||
nquery!();
|
||||
|
||||
|
@ -376,6 +408,57 @@ impl<T:Device + UrukulTraits> Command<T> for ProfileCommand {
|
|||
}
|
||||
}
|
||||
|
||||
impl<T:Device + UrukulTraits> Command<T> for Channel0Profile0Singletone {
|
||||
nquery!();
|
||||
|
||||
// Params: frequency, phase, amplitude (all mandatory)
|
||||
fn event(&self, context: &mut Context<T>, args: &mut Tokenizer) -> Result<()> {
|
||||
|
||||
// Read output frequency
|
||||
let frequency: f64::Frequency = args.next_data(false)?
|
||||
.map_or(Err(Error::new(ErrorCode::MissingParameter)), |t| {
|
||||
t.numeric(|s| match s {
|
||||
NumericValues::Default => Ok(f64::Frequency::new::<hertz>(0.0)),
|
||||
_ => Err(ErrorCode::IllegalParameterValue.into()),
|
||||
})
|
||||
})?;
|
||||
trace!("Received channel 0 profile 0 output single tone frequency: {:?}", frequency);
|
||||
// Handle negative frequency
|
||||
if frequency.get::<hertz>() < 0.0 {
|
||||
return Err(ErrorCode::DataOutOfRange.into());
|
||||
}
|
||||
|
||||
// Read phase offset
|
||||
let phase: f64::Angle = args.next_data(false)?
|
||||
.map_or(Err(Error::new(ErrorCode::MissingParameter)), |t| {
|
||||
t.numeric(
|
||||
|s| match s {
|
||||
NumericValues::Default => Ok(f64::Angle::new::<degree>(0.0)),
|
||||
_ => Err(ErrorCode::IllegalParameterValue.into()),
|
||||
})
|
||||
})?;
|
||||
trace!("Received channel 0 profile 0 output single tone phase offset: {:?}", phase);
|
||||
// Handle out-of-bound phase offset
|
||||
if phase.get::<degree>() < 0.0 || phase.get::<degree>() >= 360.0 {
|
||||
return Err(ErrorCode::DataOutOfRange.into());
|
||||
}
|
||||
|
||||
// Read amplitude offset
|
||||
let amplitude: f64 = args.next_data(false)?
|
||||
.map_or(Err(Error::new(ErrorCode::MissingParameter)),
|
||||
|token| token.try_into())?;
|
||||
trace!("Received channel 0 profile 0 output single tone amplitude offset: {:?}", amplitude);
|
||||
// Handle out-of-bound phase offset
|
||||
if amplitude < 0.0 || amplitude > 1.0 {
|
||||
return Err(ErrorCode::DataOutOfRange.into());
|
||||
}
|
||||
|
||||
// TODO: Setup single tone on DDS
|
||||
context.device.set_channel_single_tone_profile(0, 0, frequency.get::<hertz>(), phase.get::<degree>(), amplitude)
|
||||
.map_err(|_| Error::new(ErrorCode::HardwareError))
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Implement "Device" trait from SCPI
|
||||
* TODO: Implement mandatory commands
|
||||
|
|
|
@ -5,8 +5,8 @@ use log::{trace, info};
|
|||
use arrayvec::{ArrayVec};
|
||||
|
||||
pub trait MqttScpiTranslator {
|
||||
// Convert an MQTT publish message into SCPI compatible command
|
||||
// The argument part/ MQTT message must follow SCPI standard for parameter formatting
|
||||
// Unwrap an MQTT publish message into SCPI compatible command
|
||||
// The command part/ MQTT message must follow SCPI standard for parameter formatting
|
||||
fn run_with_mqtt<FMT: Formatter>(&mut self, topic: &str, args: &str, response: &mut FMT) -> Result<()>;
|
||||
}
|
||||
|
||||
|
@ -20,27 +20,27 @@ impl<'a, T: Device> MqttScpiTranslator for Context<'a, T> {
|
|||
return Ok(());
|
||||
}
|
||||
|
||||
let command_topic = topic.strip_prefix("Urukul/Control/")
|
||||
.unwrap_or("");
|
||||
// let command_topic = topic.strip_prefix("Urukul/Control")
|
||||
// .unwrap_or("");
|
||||
|
||||
// Create a fixed-size buffer to handle slice operation
|
||||
let mut buffer = ArrayVec::<[u8; 1024]>::new();
|
||||
|
||||
// Copy MQTT topic, convert it into SCPI header format
|
||||
for i in command_topic.chars() {
|
||||
if i == '/' {
|
||||
// The topic separator is colon(':') in SCPI, and slash('/') in MQTT
|
||||
buffer.try_push(b':')
|
||||
.map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
} else {
|
||||
buffer.try_push(i as u8)
|
||||
.map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
}
|
||||
}
|
||||
// // Copy MQTT topic, convert it into SCPI header format
|
||||
// for i in command_topic.chars() {
|
||||
// if i == '/' {
|
||||
// // The topic separator is colon(':') in SCPI, and slash('/') in MQTT
|
||||
// buffer.try_push(b':')
|
||||
// .map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
// } else {
|
||||
// buffer.try_push(i as u8)
|
||||
// .map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
// }
|
||||
// }
|
||||
|
||||
// Place a space bar between header and parameter
|
||||
buffer.try_push(b' ')
|
||||
.map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
// // Place a space bar between header and parameter
|
||||
// buffer.try_push(b' ')
|
||||
// .map_err(|_| ErrorCode::OutOfMemory)?;
|
||||
|
||||
// Copy the arguments into the buffer
|
||||
for i in args.chars() {
|
||||
|
|
Loading…
Reference in New Issue