forked from M-Labs/humpback-dds
scpi: fix frequency control
This commit is contained in:
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5438a81722
commit
b502b42c92
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@ -13,6 +13,7 @@ embedded-hal = "0.2.4"
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stm32h7xx-hal = {version = "0.7.1", features = [ "stm32h743v", "rt", "unproven", "ethernet", "phy_lan8742a" ] }
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smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp", "log" ] }
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nb = "1.0.0"
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libm = "0.2.0"
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embedded-nal = "0.1.0"
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minimq = { git = "https://github.com/quartiq/minimq.git", branch = "master" }
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@ -208,7 +208,7 @@ fn main() -> ! {
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let parts = switch.split();
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let mut urukul = Urukul::new(
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
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[25_000_000, 25_000_000, 25_000_000, 25_000_000]
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[25_000_000.0, 25_000_000.0, 25_000_000.0, 25_000_000.0]
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);
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// Setup ethernet pins
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@ -209,7 +209,7 @@ fn main() -> ! {
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let mut urukul = Urukul::new(
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parts.spi1, parts.spi2, parts.spi3, parts.spi4, parts.spi5, parts.spi6, parts.spi7,
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[25_000_000, 25_000_000, 25_000_000, 25_000_000]
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[25_000_000.0, 25_000_000.0, 25_000_000.0, 25_000_000.0]
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);
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cp.SCB.invalidate_icache();
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@ -75,6 +75,7 @@ where
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/*
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* Return selected configuration field
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* TODO: Return result type instead for error checking
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*/
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pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
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config_type.get_filtered_content(self.data) as u8
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45
src/dds.rs
45
src/dds.rs
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@ -1,6 +1,7 @@
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use embedded_hal::blocking::spi::Transfer;
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use crate::Error;
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use core::mem::size_of;
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use libm::round;
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/*
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* Bitmask for all configurations (Order: CFR3, CFR2, CFR1)
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@ -64,15 +65,15 @@ const READ_MASK :u8 = 0x80;
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pub struct DDS<SPI> {
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spi: SPI,
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f_ref_clk: u64,
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f_sys_clk: u64,
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f_ref_clk: f64,
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f_sys_clk: f64,
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}
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impl<SPI, E> DDS<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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pub fn new(spi: SPI, f_ref_clk: u64) -> Self {
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pub fn new(spi: SPI, f_ref_clk: f64) -> Self {
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DDS {
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spi,
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f_ref_clk,
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@ -121,7 +122,7 @@ where
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// Ensure divider is not reset
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(DDSCFRMask::REFCLK_IN_DIV_RESETB, 1),
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])?;
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self.f_sys_clk = self.f_ref_clk / 2;
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self.f_sys_clk = self.f_ref_clk / 2.0;
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Ok(())
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}
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@ -138,9 +139,9 @@ where
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Ok(())
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}
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pub fn enable_pll(&mut self, f_sys_clk: u64) -> Result<(), Error<E>> {
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pub fn enable_pll(&mut self, f_sys_clk: f64) -> Result<(), Error<E>> {
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// Get a divider
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let divider = f_sys_clk / self.f_ref_clk;
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let divider = (f_sys_clk / self.f_ref_clk) as u64;
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// Reject extreme divider values. However, accept no frequency division
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if ((divider > 127 || divider < 12) && divider != 1) {
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// panic!("Invalid divider value for PLL!");
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@ -159,14 +160,16 @@ where
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self.set_configurations(&mut [
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(DDSCFRMask::PFD_RESET, 0),
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])?;
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self.f_sys_clk = self.f_ref_clk * divider;
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self.f_sys_clk = self.f_ref_clk * (divider as f64);
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Ok(())
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}
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// Change external clock source (ref_clk)
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: u64) -> Result<(), Error<E>> {
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pub fn set_ref_clk_frequency(&mut self, f_ref_clk: f64) -> Result<(), Error<E>> {
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// Override old reference clock frequency (ref_clk)
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self.f_ref_clk = f_ref_clk;
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// TODO: Examine clock tree and update f_sys_clk
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// Calculate the new system clock frequency, examine the clock tree
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let mut configuration_queries = [
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// Acquire PLL status
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(DDSCFRMask::PLL_ENABLE, 0),
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@ -179,7 +182,7 @@ where
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self.get_configurations(&mut configuration_queries)?;
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if configuration_queries[0].1 == 1 {
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// Recalculate sys_clk
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let divider :u64 = configuration_queries[1].1.into();
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let divider :f64 = configuration_queries[1].1.into();
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let f_sys_clk = self.f_ref_clk * divider;
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// Adjust VCO
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match self.get_VCO_no(f_sys_clk, divider as u8) {
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@ -204,7 +207,7 @@ where
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}
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}
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else if configuration_queries[2].1 == 0 {
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self.f_sys_clk = self.f_ref_clk / 2;
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self.f_sys_clk = self.f_ref_clk / 2.0;
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Ok(())
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}
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else {
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@ -214,23 +217,23 @@ where
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}
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#[allow(non_snake_case)]
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fn get_VCO_no(&mut self, f_sys_clk: u64, divider: u8) -> Result<u8, Error<E>> {
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fn get_VCO_no(&mut self, f_sys_clk: f64, divider: u8) -> Result<u8, Error<E>> {
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// Select a VCO
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if divider == 1 {
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Ok(6) // Bypass PLL if no frequency division needed
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} else if f_sys_clk > 1_150_000_000 {
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} else if f_sys_clk > 1_150_000_000.0 {
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Err(Error::DDSCLKError)
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} else if f_sys_clk > 820_000_000 {
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} else if f_sys_clk > 820_000_000.0 {
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Ok(5)
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} else if f_sys_clk > 700_000_000 {
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} else if f_sys_clk > 700_000_000.0 {
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Ok(4)
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} else if f_sys_clk > 600_000_000 {
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} else if f_sys_clk > 600_000_000.0 {
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Ok(3)
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} else if f_sys_clk > 500_000_000 {
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} else if f_sys_clk > 500_000_000.0 {
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Ok(2)
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} else if f_sys_clk > 420_000_000 {
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} else if f_sys_clk > 420_000_000.0 {
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Ok(1)
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} else if f_sys_clk > 370_000_000 {
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} else if f_sys_clk > 370_000_000.0 {
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Ok(0)
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} else {
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Ok(7) // Bypass PLL if f_sys_clk is too low
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@ -311,14 +314,14 @@ where
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* Frequency: Must be integer
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* Amplitude: In a scale from 0 to 1, taking float
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*/
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pub fn set_single_tone_profile(&mut self, profile: u8, f_out: u64, phase_offset: f64, amp_scale_factor: f64) -> Result<(), Error<E>> {
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pub fn set_single_tone_profile(&mut self, profile: u8, f_out: f64, phase_offset: f64, amp_scale_factor: f64) -> Result<(), Error<E>> {
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assert!(profile < 8);
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assert!(phase_offset >= 0.0 && phase_offset < 360.0);
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assert!(amp_scale_factor >=0.0 && amp_scale_factor <= 1.0);
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let resolutions :[u64; 3] = [1 << 32, 1 << 16, 1 << 14];
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let ftw = (resolutions[0] * f_out / self.f_sys_clk) as u32;
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let ftw = ((resolutions[0] as f64) * f_out / self.f_sys_clk) as u32;
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let pow = ((resolutions[1] as f64) * phase_offset / 360.0) as u16;
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let asf :u16 = if amp_scale_factor == 1.0 {
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0x3FFF
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20
src/lib.rs
20
src/lib.rs
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@ -81,7 +81,7 @@ where
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* Master constructor for the entire Urukul device
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* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
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*/
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [u64; 4]) -> Self {
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI, f_ref_clks: [f64; 4]) -> Self {
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// Construct Urukul
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Urukul {
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config_register: ConfigRegister::new(spi1),
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@ -130,7 +130,7 @@ where
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// Clock tree reset. CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(25_000_000)?;
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self.dds[chip_no].set_ref_clk_frequency(25_000_000.0)?;
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}
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Ok(())
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}
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@ -153,7 +153,7 @@ pub trait UrukulTraits {
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type Error;
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fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Self::Error>;
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fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Self::Error>;
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fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Self::Error>;
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fn set_clock_source(&mut self, source: ClockSource, frequency: f64) -> Result<(), Self::Error>;
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fn set_clock_division(&mut self, division: u8) -> Result<(), Self::Error>;
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fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Self::Error>;
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}
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@ -190,7 +190,8 @@ where
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}
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}
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fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Self::Error> {
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fn set_clock_source(&mut self, source: ClockSource, frequency: f64) -> Result<(), Self::Error> {
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// Change clock source through configuration register
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match source {
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ClockSource::OSC => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 0),
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@ -203,7 +204,16 @@ where
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ClockSource::SMA => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 1),
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]),
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}.map(|_| ())
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}?;
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// Calculate reference clock frequency after clock division from configuration register
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let frequency = frequency / (self.config_register.get_configuration(CFGMask::DIV) as f64);
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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self.dds[dds_channel].set_ref_clk_frequency(frequency)?;
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}
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Ok(())
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}
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fn set_clock_division(&mut self, division: u8) -> Result<(), Self::Error> {
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@ -281,7 +281,7 @@ impl<T:Device + UrukulTraits> Command<T> for ClockSourceCommand {
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};
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trace!("Changing clock source to {:?} at {:?}", clock_source, frequency);
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context.device.set_clock_source(clock_source)
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context.device.set_clock_source(clock_source, frequency.get::<hertz>())
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.map_err(|_| Error::new(ErrorCode::HardwareError))
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}
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}
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@ -1,10 +1,8 @@
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use scpi::prelude::*;
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use scpi::Context;
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use scpi::error::Result;
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use core::concat;
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use arrayvec::{ArrayVec, ArrayString};
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use log::trace;
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use arrayvec::{ArrayVec};
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pub trait MqttScpiTranslator {
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// Convert an MQTT publish message into SCPI compatible command
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@ -42,6 +40,9 @@ impl<'a, T: Device> MqttScpiTranslator for Context<'a, T> {
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.map_err(|_| ErrorCode::OutOfMemory)?;
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}
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// Pass the message to SCPI processing unit
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trace!("Translated MQTT message into SCPI. Translated command: {}",
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core::str::from_utf8(buffer.as_slice()).unwrap());
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self.run(buffer.as_slice(), response)
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}
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}
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