forked from M-Labs/humpback-dds
urukul: add urukul clock config getter
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3abc0c3e4e
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@ -173,6 +173,18 @@ where
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self.set_clock_division(division)
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self.set_clock_division(division)
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}
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}
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pub fn get_clock_source(&mut self) -> Result<ClockSource, Error<E>> {
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match (
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self.config_register.get_configuration(CFGMask::CLK_SEL0),
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self.config_register.get_configuration(CFGMask::CLK_SEL1)
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) {
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(0, 0) => Ok(ClockSource::OSC),
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(0, 1) => Ok(ClockSource::MMCX),
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(1, _) => Ok(ClockSource::SMA),
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_ => Err(Error::ConfigRegisterError)
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}
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}
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pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
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pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
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// Change clock source through configuration register
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// Change clock source through configuration register
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match source {
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match source {
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@ -190,6 +202,10 @@ where
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}.map(|_| ())
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}.map(|_| ())
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}
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}
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pub fn get_clock_frequency(&mut self) -> f64 {
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self.f_master_clk
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}
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pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
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pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
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// Update master clock frequency
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// Update master clock frequency
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self.f_master_clk = frequency;
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self.f_master_clk = frequency;
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@ -198,6 +214,15 @@ where
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self.set_dds_ref_clk()
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self.set_dds_ref_clk()
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}
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}
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pub fn get_clock_division(&mut self) -> Result<u8, Error<E>> {
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match self.config_register.get_configuration(CFGMask::DIV) {
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0| 3 => Ok(4),
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1 => Ok(1),
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2 => Ok(2),
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_ => Err(Error::ConfigRegisterError)
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}
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}
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pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
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pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
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match division {
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match division {
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1 => self.config_register.set_configurations(&mut [
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1 => self.config_register.set_configurations(&mut [
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