forked from M-Labs/humpback-dds
nmigen: migrated
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# If the design does not create a "sync" clock domain, it is created by the nMigen build system
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# using the platform default clock (and default reset, if any).
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from nmigen import *
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from humpback import *
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class SimpleBlink(Elaboratable):
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def elaborate(self, platform):
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led = platform.request("user_led", 0)
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counter = Signal(24)
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pin = platform.request("gpioa", 0)
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m = Module()
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m.d.sync += counter.eq(counter + 1)
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m.d.comb += led.o.eq(counter[23])
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m.d.comb += pin.o.eq(led)
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return m
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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platform.build(SimpleBlink(), do_program=False)
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# Strongly inspired by the migen build of humpback
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# Using STM32 Nucleo-H743ZI2 board
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# Note to self: Pin assignment differs from Nucleo-H743ZI
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import os
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import subprocess
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from nmigen.build import *
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from nmigen.vendor.lattice_ice40 import *
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from nmigen_boards.resources import *
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from resources import *
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from pin_mapper import *
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__all__ = ["HumpbackPlatform"]
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class HumpbackPlatform(LatticeICE40Platform):
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device = "iCE40HX8K" # Using ICE40HX8K-CT256
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package = "CT256"
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default_clk = "clk25" # Point of deviation: Clock speed for humpback is fixed at 25MHz
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# Acquire GPIO mappings from gpio_mapper
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gpio_dict, global_gpio_dict = GPIOMapping()
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resources = [
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# Define clock
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Resource("clk25", 0, Pins("K9", dir="i"),
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Clock(25e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")
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),
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# Define user LED
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Resource("user_led", 0, Pins("H3", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")
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),
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# Serial interfaces: Only including pins usable to STM32
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# Define UART interfaces
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# UART interface: There are no pull ups from humpback.
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# Need to configure STM32 pins to pull up.
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# Note: Use USART in asynchronous mode
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UARTResource(0,
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rx="T11", tx="M13", rts="M15", cts="T10",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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# UART1 interface: Read note for UART interface above
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# UART1 interface is broken due to pin rearrangement introduced for Nucleo-H743ZI2
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# Uncomment if fixed, or found an alternative (e.g. bit banging UART)
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# *UARTResource(1,
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# tx="M11", rx="T13", rts="A6", cts="B16",
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# attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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# ),
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# Define SPI interfaces
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# Note: Use "role=device" to make humpback a SPI slave
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# The ~CS pin is a global pin, but not being configured global.
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SPIResource(0,
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cs="R2", clk="C8", mosi="N5", miso="T2",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS")
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),
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# Define I2C interface
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# Note: Need to program pull up in stm32
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# Use "role=device" to make humpback a I2C slave
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I2CResource(0,
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sda="T16", scl="M12",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
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),
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# TODO:STM32 GPIO pins, ignore other unusable pins as well
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*GPIOResources(
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pins_dict = gpio_dict, dir = "o",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
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),
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*GPIOResources(
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pins_dict = global_gpio_dict, dir = "o",
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attrs=Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS"),
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),
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]
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connectors = []
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# tool chain setup, using default ICE40 HX8K evaluation code
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def toolchain_program(self, products, name):
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iceprog = os.environ.get("ICEPROG", "iceprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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# TODO: this should be factored out and made customizable
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subprocess.check_call([iceprog, "-S", bitstream_filename])
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if __name__ == "__main__":
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from nmigen_boards.test.blinky import *
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HumpbackPlatform().build(Blinky(), do_program=False)
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import pandas as pd
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# Get dictionaries of:
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# - Non-global GPIO to FPGA mapping
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# - Global GPIO to FPGA mapping
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# (Ordered)
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def GPIOMapping():
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# Standard extraction of data from excel file
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data = pd.read_excel("nmigen/FPGA_pins.xlsx", skiprows = range(1,2))
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df = pd.DataFrame(data, columns=["Designator", "Pin Name", "Net"])
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stm32 = df[df.Net.str.startswith("STM32")]
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# Change some GPIO mapping for Nucleo-H743ZI2
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# Created a mapping from old pins to new pins
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old_to_new_dict = {
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# Old : New
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"PC1" :"PB1" ,
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"PC4" :"PC2" ,
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"PC5" :"PF10" ,
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"PA1" :"PB2" ,
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"PA7" :"PE9" ,
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"PA8" :"PF2" ,
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"PA9" :"PF1" ,
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"PA10" :"PF0" ,
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"PB1" :"PF4" ,
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"PC2" :"PF5" ,
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"PA2" :"PF6" ,
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"PB6" :"PG6" ,
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"PE13" :"PG12" ,
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"PF14" :"PE14" ,
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"PE14" :"PE6" ,
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}
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# Extract data from stm32 dataframe to a dictionary
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gpio_dict = {}
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global_gpio_dict = {}
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for index, row in stm32.iterrows():
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# Replace old pins with new pins
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# Note: There are 2 PE6 pins on Nucleo-H743ZI2
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# This will remove 1 mapping of PE6, keys cannot be duplicated
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key = row["Net"].split("_")[1]
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if key in old_to_new_dict:
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key = old_to_new_dict.pop(key)
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dict_entry = {key: row["Designator"]}
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# Insert mappings into dictionary
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if "BIN" in row["Pin Name"]:
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global_gpio_dict.update(dict_entry)
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else:
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gpio_dict.update(dict_entry)
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return gpio_dict, global_gpio_dict
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# Function to provide mapping EEM pins to differential pins
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# Usage:
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# Positive pin: <returned>[<eem_port_val>][<eem_port_ldvs_num>][0]
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# Negative pin: <returned>[<eem_port_val>][<eem_port_ldvs_num>][1]
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def diffMapping():
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eem0 = [
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# P+ve , N-ve
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[ "J3" , "H1" ],
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[ "F5" , "B1" ],
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[ "C1" , "C2" ],
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[ "F4" , "D2" ],
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[ "G5" , "D1" ],
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[ "G4" , "E3" ],
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[ "H5" , "E2" ],
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[ "G3" , "F3" ],
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]
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eem1 = [
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# P+ve , N-ve
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[ "L6" , "L3" ],
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[ "H6" , "F1" ],
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[ "H4" , "G2" ],
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[ "J4" , "H2" ],
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[ "J2" , "J1" ],
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[ "K1" , "K3" ],
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[ "L4" , "L1" ],
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[ "K4" , "M1" ],
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]
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eem2 = [
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# P+ve , N-ve
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[ "J5" , "G1" ],
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[ "K5" , "M2" ],
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[ "L7" , "N2" ],
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[ "M6" , "M3" ],
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[ "L5" , "N3" ],
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[ "P1" , "M4" ],
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[ "P2" , "M5" ],
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[ "R1" , "N4" ],
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]
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return [eem0, eem1, eem2]
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from nmigen.build import *
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__all__ = ["I2CResource", "GPIOResources", "DiffResources"]
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def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"):
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assert role in ("host", "device")
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io = []
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# sda line: I/O port for the data line
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io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1)))
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# sck line: I2C clock signal outputs from master to slave
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if role == "host":
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io.append(Subsignal("scl", Pins(scl, dir="o", conn=conn, assert_width=1)))
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else: #device
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io.append(Subsignal("scl", Pins(scl, dir="i", conn=conn, assert_width=1)))
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if attrs is not None:
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io.append(attrs)
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return Resource.family(*args, default_name="i2c", ios=io)
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# Auto create a resource list given a set of iCE40 pins and STM32 pin names (pins_dict)
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def GPIOResources(*args, pins_dict, dir = "o", invert=False, conn=None, attrs=None):
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# Check data integrity: pins_dict must be a dict AND port must be from a to k
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assert isinstance(pins_dict, dict)
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# Debug: dir == "o"
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assert dir == "o"
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# List of resources to be returned
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resources = []
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for STM32_pin, iCE40_pin in pins_dict.items():
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# Set all gpio pins to be output only for the time being
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# TODO: Allow dir argument.
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ios = [Pins(iCE40_pin, dir=dir, invert=invert, conn=conn)]
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if attrs is not None:
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ios.append(attrs)
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# Extract GPIO port and port number from STM32_pin
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# Strip "P" from P<port><port_num>
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if STM32_pin.startswith('P'):
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STM32_pin = STM32_pin[1:]
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# Acquire port from <port><port_num>
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port = STM32_pin[0].lower()
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port_num = int(STM32_pin[1:])
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# Insert gpio<port>.<portNum> into resources list
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resources.append(Resource.family(*args, port_num, default_name=("gpio"+port), ios=ios))
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return resources
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# Auto create a resource list for differential I/O
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def DiffResources(*args, eem_pins, invert=False, conn=None, attrs=None, dir):
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# TODO: Everything
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# assert dimensionality
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assert isinstance(eem_pins, list)
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assert isinstance(eem_pins[0], list)
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assert isinstance(eem_pins[0][0], list)
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assert isinstance(eem_pins[0][0][0], str)
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# assert direction to be either input or output
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# reject tristate or bidirectional pin
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assert dir in ("i", "o")
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if __name__ == "__main__":
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from pin_mapper import *
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eem = diffMapping()
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DiffResources(eem_pins = eem, dir = "o",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS")
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)
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