cpld: fix indent

This commit is contained in:
occheung 2020-08-31 09:34:38 +08:00
parent 4852fc54ea
commit 69761c4517
1 changed files with 152 additions and 152 deletions

View File

@ -11,155 +11,155 @@ use core::cell;
/* /*
* Basic structure for CPLD signal multiplexing * Basic structure for CPLD signal multiplexing
*/ */
#[derive(Debug)] #[derive(Debug)]
pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> { pub struct CPLDData<SPI, CS0, CS1, CS2, GPIO> {
pub(crate) spi: SPI, pub(crate) spi: SPI,
pub(crate) chip_select: (CS0, CS1, CS2), pub(crate) chip_select: (CS0, CS1, CS2),
pub(crate) io_update: GPIO, pub(crate) io_update: GPIO,
} }
#[derive(Debug)] #[derive(Debug)]
pub struct CPLD<SPI, CS0, CS1, CS2, GPIO> { pub struct CPLD<SPI, CS0, CS1, CS2, GPIO> {
pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2, GPIO>>, pub(crate) data: cell::RefCell<CPLDData<SPI, CS0, CS1, CS2, GPIO>>,
} }
pub trait SelectChip { pub trait SelectChip {
type Error; type Error;
fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error>; fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error>;
} }
impl<SPI, CS0, CS1, CS2, GPIO, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2, GPIO> impl<SPI, CS0, CS1, CS2, GPIO, E> SelectChip for CPLDData<SPI, CS0, CS1, CS2, GPIO>
where where
SPI: Transfer<u8, Error = E>, SPI: Transfer<u8, Error = E>,
CS0: OutputPin, CS0: OutputPin,
CS1: OutputPin, CS1: OutputPin,
CS2: OutputPin, CS2: OutputPin,
GPIO: OutputPin, GPIO: OutputPin,
{ {
type Error = Error<E>; type Error = Error<E>;
fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> { fn select_chip(&mut self, chip: u8) -> Result<(), Self::Error> {
match chip & (1 << 0) { match chip & (1 << 0) {
0 => self.chip_select.0.set_low(), 0 => self.chip_select.0.set_low(),
_ => self.chip_select.0.set_high(), _ => self.chip_select.0.set_high(),
}.map_err(|_| Error::CSError)?; }.map_err(|_| Error::CSError)?;
match chip & (1 << 1) { match chip & (1 << 1) {
0 => self.chip_select.1.set_low(), 0 => self.chip_select.1.set_low(),
_ => self.chip_select.1.set_high(), _ => self.chip_select.1.set_high(),
}.map_err(|_| Error::CSError)?; }.map_err(|_| Error::CSError)?;
match chip & (1 << 2) { match chip & (1 << 2) {
0 => self.chip_select.2.set_low(), 0 => self.chip_select.2.set_low(),
_ => self.chip_select.2.set_high(), _ => self.chip_select.2.set_high(),
}.map_err(|_| Error::CSError)?; }.map_err(|_| Error::CSError)?;
Ok(()) Ok(())
} }
} }
pub trait IssueIOUpdate { pub trait IssueIOUpdate {
type Error; type Error;
fn issue_io_update(&mut self) -> Result<(), Self::Error>; fn issue_io_update(&mut self) -> Result<(), Self::Error>;
} }
impl<SPI, CS0, CS1, CS2, GPIO, E> IssueIOUpdate for CPLDData<SPI, CS0, CS1, CS2, GPIO> impl<SPI, CS0, CS1, CS2, GPIO, E> IssueIOUpdate for CPLDData<SPI, CS0, CS1, CS2, GPIO>
where where
SPI: Transfer<u8>, SPI: Transfer<u8>,
CS0: OutputPin, CS0: OutputPin,
CS1: OutputPin, CS1: OutputPin,
CS2: OutputPin, CS2: OutputPin,
GPIO: OutputPin<Error = E>, GPIO: OutputPin<Error = E>,
{ {
type Error = Error<E>; type Error = Error<E>;
fn issue_io_update(&mut self) -> Result<(), Self::Error> { fn issue_io_update(&mut self) -> Result<(), Self::Error> {
self.io_update.set_high().map_err(|_| Error::IOUpdateError)?; self.io_update.set_high().map_err(|_| Error::IOUpdateError)?;
self.io_update.set_low().map_err(|_| Error::IOUpdateError) self.io_update.set_low().map_err(|_| Error::IOUpdateError)
} }
} }
pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> { pub trait DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> {
fn do_on_get_ref_mut_data<R, E>( fn do_on_get_ref_mut_data<R, E>(
&self, &self,
f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>, f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
) -> Result<R, Error<E>>; ) -> Result<R, Error<E>>;
} }
impl<SPI, CS0, CS1, CS2, GPIO> DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> for CPLD<SPI, CS0, CS1, CS2, GPIO> { impl<SPI, CS0, CS1, CS2, GPIO> DoOnGetRefMutData<SPI, CS0, CS1, CS2, GPIO> for CPLD<SPI, CS0, CS1, CS2, GPIO> {
fn do_on_get_ref_mut_data<R, E>( fn do_on_get_ref_mut_data<R, E>(
&self, &self,
f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>, f: impl FnOnce(cell::RefMut<CPLDData<SPI, CS0, CS1, CS2, GPIO>>) -> Result<R, Error<E>>,
) -> Result<R, Error<E>> { ) -> Result<R, Error<E>> {
let dev = self let dev = self
.data .data
.try_borrow_mut() .try_borrow_mut()
.map_err(|_| Error::GetRefMutDataError)?; .map_err(|_| Error::GetRefMutDataError)?;
f(dev) f(dev)
} }
} }
impl<SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2, GPIO> impl<SPI, CS0, CS1, CS2, GPIO, E> Transfer<u8> for CPLD<SPI, CS0, CS1, CS2, GPIO>
where where
SPI: Transfer<u8, Error = E>, SPI: Transfer<u8, Error = E>,
CS0: OutputPin, CS0: OutputPin,
CS1: OutputPin, CS1: OutputPin,
CS2: OutputPin, CS2: OutputPin,
GPIO: OutputPin, GPIO: OutputPin,
{ {
type Error = Error<E>; type Error = Error<E>;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
self.do_on_get_ref_mut_data(move |mut dev| dev.spi.transfer(words).map_err(Error::SPI)) self.do_on_get_ref_mut_data(move |mut dev| dev.spi.transfer(words).map_err(Error::SPI))
} }
} }
impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> where impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> where
SPI: Transfer<u8, Error = E>, SPI: Transfer<u8, Error = E>,
CS0: OutputPin, CS0: OutputPin,
CS1: OutputPin, CS1: OutputPin,
CS2: OutputPin, CS2: OutputPin,
GPIO: OutputPin GPIO: OutputPin
{ {
// Constructor for CPLD // Constructor for CPLD
pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self { pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2), io_update: GPIO) -> Self {
// Init data // Init data
let data = CPLDData { let data = CPLDData {
spi, spi,
chip_select, chip_select,
io_update, io_update,
}; };
// Init CPLD // Init CPLD
CPLD { CPLD {
data: cell::RefCell::new(data), data: cell::RefCell::new(data),
} }
} }
// Destroy the wrapper, return the CPLD data // Destroy the wrapper, return the CPLD data
pub fn destroy(self) -> (SPI, (CS0, CS1, CS2), GPIO) { pub fn destroy(self) -> (SPI, (CS0, CS1, CS2), GPIO) {
let cpld = self.data.into_inner(); let cpld = self.data.into_inner();
(cpld.spi, cpld.chip_select, cpld.io_update) (cpld.spi, cpld.chip_select, cpld.io_update)
} }
// Split SPI into chips, wrapped by Parts struct // Split SPI into chips, wrapped by Parts struct
pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO> { pub fn split<'a>(&'a self) -> Parts<'a, CPLD<SPI, CS0, CS1, CS2, GPIO>, SPI, CS0, CS1, CS2, GPIO> {
Parts::new(&self) Parts::new(&self)
} }
// Select Chip // Select Chip
pub fn select_chip(&mut self, channel: u8) -> Result<(), Error<E>> { pub fn select_chip(&mut self, channel: u8) -> Result<(), Error<E>> {
self.do_on_get_ref_mut_data(|mut dev| dev.select_chip(channel)) self.do_on_get_ref_mut_data(|mut dev| dev.select_chip(channel))
} }
} }
impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO> impl<SPI, CS0, CS1, CS2, GPIO, E> CPLD<SPI, CS0, CS1, CS2, GPIO>
where where
SPI: Transfer<u8>, SPI: Transfer<u8>,
CS0: OutputPin, CS0: OutputPin,
CS1: OutputPin, CS1: OutputPin,
CS2: OutputPin, CS2: OutputPin,
GPIO: OutputPin<Error = E> GPIO: OutputPin<Error = E>
{ {
// Issue I/O Update // Issue I/O Update
pub fn issue_io_update(&mut self) -> Result<(), Error<E>> { pub fn issue_io_update(&mut self) -> Result<(), Error<E>> {
self.do_on_get_ref_mut_data(|mut dev| dev.issue_io_update()) self.do_on_get_ref_mut_data(|mut dev| dev.issue_io_update())
} }
} }