forked from M-Labs/humpback-dds
flash: init abstraction
This commit is contained in:
parent
d6fdc36c78
commit
68d58857cf
442
src/flash.rs
442
src/flash.rs
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@ -1,64 +1,408 @@
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use heapless::{String, consts::*};
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use smoltcp as net;
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use embedded_nal as nal;
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use core::str::FromStr;
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//! Flash memory, with major reference from STM32F7xx_HAL crate,
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//! as well as @Astro 's work in STM32F4xx_HAL
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unsafe fn read_record_length(addr: u32) -> u32 {
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core::ptr::read(addr as *const u32)
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use stm32h7xx_hal::pac::FLASH;
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/// Base address of flash memory on AXIM interface.
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const FLASH_BASE: *mut u8 = 0x800_0000 as *mut u8;
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/// The last valid flash address in STM32H743
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const MAX_FLASH_ADDRESS: *mut u8 = 0x81F_FFFF as *mut u8;
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/// Flash programming error.
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#[derive(Debug, PartialEq, Eq)]
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pub enum Error {
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Busy,
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Locked,
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WriteProtection,
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ProgrammingSequence,
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Strobe,
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Inconsistency,
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Operation,
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ErrorCorrectionCode,
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ReadProtection,
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ReadSecure,
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WriteError
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}
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unsafe fn read_byte(addr: u32) -> u8 {
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core::ptr::read(addr as *const u8)
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/// Embedded flash memory.
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pub struct Flash {
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registers: FLASH,
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}
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fn read_flash_str(addr: &mut u32) -> (String<U32>, String<U64>) {
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let mut key: String<U32> = String::new();
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let mut string: String<U64> = String::new();
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let record_length = unsafe {
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read_record_length(*addr)
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};
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if record_length == 0xFFFFFFFF {
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return (key, string);
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impl Flash {
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/// Creates a new Flash instance.
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pub fn new(flash: FLASH) -> Self {
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let mut flash = Self { registers: flash };
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// Lock both banks initially
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flash.lock();
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flash
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}
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let mut key_string_div = false;
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for f_addr in (*addr)+4..((*addr)+record_length) {
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if key_string_div {
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string.push(unsafe {read_byte(f_addr)} as char).unwrap();
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} else {
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let c = unsafe {read_byte(f_addr)};
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if c == 0 {
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key_string_div = true;
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} else {
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key.push(c as char).unwrap();
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/// Unlocks the FLASH_CR1/2 register.
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pub fn unlock(&mut self) {
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// Note: Unlocking an unlocked bank will cause HardFault
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// Unlock bank 1 if needed.
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if self.bank1_is_locked() {
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self.registers.bank1_mut().keyr.write(|w| unsafe {
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w.keyr().bits(0x45670123)
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});
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self.registers.bank1_mut().keyr.write(|w| unsafe {
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w.keyr().bits(0xCDEF89AB)
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});
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}
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// Unlock bank 2 if needed.
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if self.bank2_is_locked() {
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self.registers.bank2_mut().keyr.write(|w| unsafe {
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w.keyr().bits(0x45670123)
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});
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self.registers.bank2_mut().keyr.write(|w| unsafe {
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w.keyr().bits(0xCDEF89AB)
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});
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}
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}
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/// Unlocks the FLASH_OPTCR register
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pub fn unlock_optcr(&mut self) {
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if self.optcr_is_locked() {
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self.registers.optkeyr_mut().write(|w| unsafe {
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w.optkeyr().bits(0x08192A3B)
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});
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self.registers.optkeyr_mut().write(|w| unsafe {
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w.optkeyr().bits(0x4C5D6E7F)
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});
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}
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}
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/// Locks the FLASH_CR1/2 register.
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pub fn lock(&mut self) {
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self.registers.bank1_mut().cr.modify(|_, w| w.lock().set_bit());
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self.registers.bank2_mut().cr.modify(|_, w| w.lock().set_bit());
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}
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/// Lock the FLASH_OPTCR register
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pub fn lock_optcr(&mut self) {
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self.registers.optcr_mut().modify(|_, w| w.optlock().set_bit());
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}
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// More literal methods to get bank status
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fn bank1_is_locked(&self) -> bool {
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self.registers.bank1_mut().cr.read().lock().bit_is_set()
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}
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fn bank2_is_locked(&self) -> bool {
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self.registers.bank2_mut().cr.read().lock().bit_is_set()
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}
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fn optcr_is_locked(&self) -> bool {
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self.registers.optcr().read().optlock().bit_is_set()
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}
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pub fn is_locked(&self) -> bool {
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self.bank1_is_locked() || self.bank2_is_locked()
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}
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/// Returns `true` if a write/erase operation is in progress.
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fn is_busy(&self) -> bool {
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let (sr1, sr2) = (
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self.registers.bank1_mut().sr.read(),
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self.registers.bank2_mut().sr.read()
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);
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sr1.bsy().bit_is_set() || sr2.bsy().bit_is_set()
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}
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/// Returns `true` if a write/erase operation is in a command queue buffer.
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fn is_queuing(&self) -> bool {
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let (sr1, sr2) = (
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self.registers.bank1_mut().sr.read(),
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self.registers.bank2_mut().sr.read()
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);
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sr1.qw().bit_is_set() || sr2.qw().bit_is_set()
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}
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/// Returns `true` if write buffer is not empty in bank 1
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fn bank1_is_buffering(&self) -> bool {
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let sr1 = self.registers.bank1_mut().sr.read();
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sr1.wbne().bit_is_set()
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}
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/// Returns `true` if write buffer is not empty in bank 2
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fn bank2_is_buffering(&self) -> bool {
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let sr2 = self.registers.bank2_mut().sr.read();
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sr2.wbne().bit_is_set()
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}
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/// Erase a sector.
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pub fn erase_sector(&mut self, bank_number: u8, sector_number: u8) -> Result<(), Error> {
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// Assert parameters validity
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assert!(bank_number == 1 || bank_number == 2);
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assert!(sector_number < 8);
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// 1. Check & clear error flags
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self.clear_errors();
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// 2. Unlock FLASH_CR1/2 register if necessary
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self.unlock();
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// 3. Set SER1/2 & SNB1/2 bits in FLASH_CR1/2 register
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// 4. Set START1/2 bit in FLASH_CR1/2 register
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match bank_number {
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1 => {
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self.registers.bank1_mut().cr.modify(|_, w| unsafe {
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w.ser()
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.set_bit()
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.snb()
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.bits(sector_number)
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});
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self.registers.bank1_mut().cr.modify(|_, w| {
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w.start().set_bit()
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});
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},
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2 => {
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self.registers.bank2_mut().cr.modify(|_, w| unsafe {
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w.ser()
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.set_bit()
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.snb()
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.bits(sector_number)
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});
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self.registers.bank2_mut().cr.modify(|_, w| {
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w.start().set_bit()
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});
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},
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_ => unreachable!()
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}
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// Lock the flash CR again
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self.lock();
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Ok(())
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}
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/// Erase a bank.
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pub fn erase_bank(&mut self, bank_number: u8) -> Result<(), Error> {
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// Assert parameters validity
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assert!(bank_number == 1 || bank_number == 2);
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// 1. Check & clear error flags
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self.clear_errors();
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// 2. Unlock FLASH_CR1/2 register if necessary
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self.unlock();
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// 3 & 4. Set BER1/2 bit and START1/2 bit in FLASH_CR1/2 register
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// Wait until the corresponding QW1/2 bit is cleared.
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// Note: By setting BER1/2 bit alongside START1/2,
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// mass erase is invoked since it supersedes sector erase.
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match bank_number {
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1 => {
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self.registers.bank1_mut().cr.modify(|_, w| {
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w.ber()
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.set_bit()
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.start()
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.set_bit()
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});
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while self.registers.bank1_mut().sr.read().qw().bit_is_set() {}
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},
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2 => {
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self.registers.bank2_mut().cr.modify(|_, w| {
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w.ber()
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.set_bit()
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.start()
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.set_bit()
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});
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while self.registers.bank2_mut().sr.read().qw().bit_is_set() {}
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},
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_ => unreachable!()
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}
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// Lock the flash CR again
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self.lock();
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Ok(())
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}
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/// Mass erases of the flash memory.
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pub fn mass_erase(&mut self) -> Result<(), Error> {
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// 1. Check & clear error flags
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self.clear_errors();
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// 2. Unlock Flash_CR1&2, FLASH_OPTCR registers
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self.unlock();
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self.unlock_optcr();
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// 3. Set MER in FLASH_OPTCR to 1, wait until both QW to clear
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self.registers.optcr_mut().modify(|_, w| {
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w.mer().set_bit()
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});
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while self.is_queuing() {}
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// Lock the flash CR and OPTCR again
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self.lock();
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self.lock_optcr();
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Ok(())
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}
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/// Program flash words (32-bytes).
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/// Flashing incomplete flash word is "tolerated", but you have been warned..
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pub fn program<'a, 'b>(
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&'a mut self,
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start_offset: usize,
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data: &'b [u8],
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) -> Result<(), Error> {
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if (start_offset % 32 != 0) || (data.len() % 32 != 0) {
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log::warn!("Warning: This flash operation might not be supported...");
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log::warn!("Consider force writing the data in buffer...");
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}
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self.clear_errors();
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// Invoke single writes per 32-bytes row
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let mut current_address = start_offset;
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let mut remaining_data = data;
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while remaining_data.len() != 0 {
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let single_write_size = 32 - (current_address % 32);
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// Determine the index that split the coming row and the remaining bytes.
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let splitting_index = core::cmp::min(
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single_write_size,
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remaining_data.len()
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);
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let single_row_data = &remaining_data[..splitting_index];
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// 1. Unlock FLASH_CR1/2 register if necessary
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self.unlock();
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// 2. Set PG bit in FLASH_CR1/2
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self.registers.bank1_mut().cr.modify(|_, w| {
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w.pg().set_bit()
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});
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self.registers.bank2_mut().cr.modify(|_, w| {
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w.pg().set_bit()
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});
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// 3. Check Protection
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// There should not be any data protection anyway...
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// 4. Write data byte by byte
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for (index, byte) in single_row_data.iter().enumerate() {
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while self.is_busy() {}
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match self.check_errors() {
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Ok(_) => {
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let address: *mut u8 = unsafe {
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FLASH_BASE.add(current_address + index)
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};
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if address > MAX_FLASH_ADDRESS {
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self.registers.bank1_mut().cr.modify(|_, w| w.pg().clear_bit());
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self.registers.bank2_mut().cr.modify(|_, w| w.pg().clear_bit());
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return Err(Error::WriteError);
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} else {
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unsafe {
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core::ptr::write_volatile(address, *byte);
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}
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}
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},
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Err(error) => {
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self.registers.bank1_mut().cr.modify(|_, w| w.pg().clear_bit());
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self.registers.bank2_mut().cr.modify(|_, w| w.pg().clear_bit());
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return Err(error);
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}
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}
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}
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// 5. Wait till the command queue of the device to be empty
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while self.is_queuing() {}
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// Modify remaining data and the address for next 32-bytes row.
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remaining_data = &remaining_data[splitting_index..];
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current_address += single_row_data.len();
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}
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// Reset PG1/2
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self.registers.bank1_mut().cr.modify(|_, w| w.pg().clear_bit());
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self.registers.bank2_mut().cr.modify(|_, w| w.pg().clear_bit());
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// Lock FLASH_CR1/2 register
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self.lock();
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Ok(())
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}
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*addr += record_length;
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(key, string)
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}
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pub fn read_flash(addr: &mut u32)
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-> (net::wire::IpCidr, net::wire::EthernetAddress, nal::Ipv4Addr, String<U64>)
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{
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let mut cidr = net::wire::IpCidr::Ipv6(
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net::wire::Ipv6Cidr::SOLICITED_NODE_PREFIX,
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);
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let mut eth = net::wire::EthernetAddress::BROADCAST;
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let mut ip = nal::Ipv4Addr::unspecified();
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let mut name = String::new();
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loop {
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let (key, string) = read_flash_str(addr);
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if key.len() == 0 {
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return (cidr, eth, ip, name);
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/// Force empty the bytes buffer for flash programming
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/// Warning: It can invalidate the whole flash due to invalid CRC.
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pub fn force_write<'a>(
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&'a mut self
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) -> Result<(), Error> {
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if self.bank1_is_buffering() {
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self.registers.bank1_mut().cr.modify(
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|_, w| w.fw().set_bit()
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);
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}
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match key.as_str() {
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"CIDR" => cidr = net::wire::IpCidr::from_str(&string).unwrap(),
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"MAC" => eth = net::wire::EthernetAddress::from_str(&string).unwrap(),
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"BrokerIP" => ip = nal::Ipv4Addr::from_str(&string).unwrap(),
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"Name" => name = string,
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_ => {},
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if self.bank2_is_buffering() {
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self.registers.bank2_mut().cr.modify(
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|_, w| w.fw().set_bit()
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);
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}
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Ok(())
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}
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/// Read a slice from flash memory
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pub fn read(&self, start_offset: usize, len: usize) -> &'static [u8] {
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let address = unsafe {
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FLASH_BASE.add(start_offset)
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};
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unsafe { core::slice::from_raw_parts(address, len) }
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}
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/// Releases the flash peripheral.
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pub fn free(self) -> FLASH {
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self.registers
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}
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/// Checks the error flags.
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fn check_errors(&self) -> Result<(), Error> {
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let (sr1, sr2) = (
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self.registers.bank1_mut().sr.read(),
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self.registers.bank2_mut().sr.read()
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);
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if sr1.wrperr().bit_is_set() || sr2.wrperr().bit_is_set() {
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Err(Error::WriteProtection)
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} else if sr1.pgserr().bit_is_set() || sr2.pgserr().bit_is_set() {
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Err(Error::ProgrammingSequence)
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} else if sr1.strberr().bit_is_set() || sr2.strberr().bit_is_set() {
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Err(Error::Strobe)
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} else if sr1.incerr().bit_is_set() || sr2.incerr().bit_is_set() {
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Err(Error::Inconsistency)
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} else if sr1.operr().bit_is_set() || sr2.operr().bit_is_set() {
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Err(Error::Operation)
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} else if sr1.sneccerr1().bit_is_set() || sr1.dbeccerr().bit_is_set()
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|| sr2.sneccerr1().bit_is_set() || sr2.dbeccerr().bit_is_set() {
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Err(Error::ErrorCorrectionCode)
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} else if sr1.rdperr().bit_is_set() || sr2.rdperr().bit_is_set() {
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Err(Error::ReadProtection)
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} else if sr1.rdserr().bit_is_set() || sr2.rdserr().bit_is_set() {
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Err(Error::ReadSecure)
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} else {
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Ok(())
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}
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}
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/// Clears all error flags.
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fn clear_errors(&mut self) {
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self.registers.bank1_mut().ccr.write(|w| {
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w.clr_wrperr()
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.set_bit()
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.clr_pgserr()
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.set_bit()
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.clr_strberr()
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.set_bit()
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.clr_incerr()
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.set_bit()
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.clr_operr()
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.set_bit()
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.clr_rdperr()
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.set_bit()
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.clr_rdserr()
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.set_bit()
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.clr_sneccerr()
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.set_bit()
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.clr_dbeccerr()
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.set_bit()
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});
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self.registers.bank2_mut().ccr.write(|w| {
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w.clr_wrperr()
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.set_bit()
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.clr_pgserr()
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.set_bit()
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.clr_strberr()
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.set_bit()
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.clr_incerr()
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.set_bit()
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.clr_operr()
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.set_bit()
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.clr_rdperr()
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.set_bit()
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.clr_rdserr()
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.set_bit()
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.clr_sneccerr()
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.set_bit()
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.clr_dbeccerr()
|
||||
.set_bit()
|
||||
});
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue