forked from M-Labs/humpback-dds
cpld: basic switching capability
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393138dc9a
commit
58e77ae671
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@ -1,5 +1,5 @@
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[target.thumbv7em-none-eabihf]
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runner = "gdb -q -x gdb_config/debug.gdb"
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runner = "gdb -q -x gdb_config/fpga_config.gdb"
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rustflags = [
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"-C", "link-arg=-Tlink.x",
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]
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@ -22,14 +22,14 @@ class UrukulConnector(Module):
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self.comb += [
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eem.p[0].eq(spi.sclk),
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eem.p[1].eq(spi.mosi),
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eem.p[2].eq(spi.miso),
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spi.miso.eq(eem.p[2]),
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eem.p[3].eq(spi.cs[0]),
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eem.p[4].eq(spi.cs[1]),
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eem.p[5].eq(spi.cs[2]),
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]
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# Debug purposes: Tie MISO to MOSI
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self.comb += spi.miso.eq(spi.mosi)
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# Debug purposes: Tie EEM MISO to EEM MOSI
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# self.comb += eem.p[2].eq(eem.n[1])
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if __name__ == "__main__":
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@ -1,112 +0,0 @@
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#![no_main]
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#![no_std]
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extern crate panic_itm;
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use stm32h7xx_hal::hal::digital::v2::OutputPin;
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use stm32h7xx_hal::{pac, prelude::*};
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use cortex_m_rt::entry;
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use cortex_m_log::println;
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use cortex_m_log::{
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destination::Itm, printer::itm::InterruptSync as InterruptSyncItm,
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};
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/*
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* I2C Address of the I2C switch (TCA9548ARGER)
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*/
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const TCA9548ARGER_ADDR :u8 = 0x72;
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/*
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* Control register bit masks
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*/
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const CHANNEL_0 :u8 = 0x01;
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const CHANNEL_1 :u8 = 0x02;
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const CHANNEL_2 :u8 = 0x04;
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const CHANNEL_3 :u8 = 0x08;
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const CHANNEL_4 :u8 = 0x10;
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const CHANNEL_5 :u8 = 0x20;
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const CHANNEL_6 :u8 = 0x40;
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const CHANNEL_7 :u8 = 0x80;
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/*
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* I2C Address of slaves at different channels
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*/
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const TEMP_1_ADDR :u8 = 0x48;
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const TEMP_PRODUCT_ID_REG :u8 = 0x07;
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#[entry]
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fn main() -> ! {
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let cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let mut log = InterruptSyncItm::new(Itm::new(cp.ITM));
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// Constrain and Freeze power
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// println!(log, "Setup PWR... ");
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Constrain and Freeze clock
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// println!(log, "Setup RCC... ");
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let rcc = dp.RCC.constrain();
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let ccdr = rcc.sys_ck(100.mhz()).freeze(vos, &dp.SYSCFG);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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// Configure the SCL and the SDA pin for our I2C bus
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let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
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let sda = gpiob.pb9.into_alternate_af4().set_open_drain();
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let mut i2c =
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dp.I2C1
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.i2c((scl, sda), 100.khz(), ccdr.peripheral.I2C1, &ccdr.clocks);
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// Setup delay
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let mut delay = cp.SYST.delay(ccdr.clocks);
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// Configure led
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let mut green = gpiob.pb0.into_push_pull_output();
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let mut yellow = gpioe.pe1.into_push_pull_output();
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let mut red = gpiob.pb14.into_push_pull_output();
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// I2C switch (TCA9548ARGER_ADDR): Only enable channel 5
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let mut tx1 :[u8, 1] = [CHANNEL_5];
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let mut rx1 :[u8; 1] = [0];
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loop {
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i2c.write(TCA9548ARGER_ADDR, &tx1);
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delay.delay_ms(10_u16);
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}
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// Read back the control value
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i2c.read(TCA9548ARGER_ADDR, &mut rx1).unwrap();
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// Match the control register content with the CHANNEL_5 mask
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match rx1[0] {
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CHANNEL_5 => yellow.set_high(),
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_ => yellow.set_low(),
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}.unwrap();
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loop {
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red.set_high().unwrap();
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}
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// delay.delay_ms(100_u16);
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// Temperature sensor (TEMP_1_ADDR): write TEMP_PRODUCT_ID_REG, and read its content (1 byte)
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let mut tx2 :[u8, 1] = TEMP_PRODUCT_ID_REG;
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let mut rx2 :[u8; 1] = [0];
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// i2c.write_read(TEMP_1_ADDR, &tx1.clone(), &mut rx).unwrap();
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i2c.write_read(TCA9548ARGER_ADDR, &tx2.clone(), &mut rx2).unwrap();
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// The ID should be 0xA1.
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match rx2[0] {
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0xA1 => green.set_high(),
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_ => green.set_low(),
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}.unwrap();
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loop {
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red.set_high().unwrap();
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}
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}
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@ -1,76 +0,0 @@
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#![deny(warnings)]
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#![deny(unsafe_code)]
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#![no_main]
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#![no_std]
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extern crate panic_itm;
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use cortex_m;
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use cortex_m_rt::entry;
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use stm32h7xx_hal::hal::digital::v2::OutputPin;
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use stm32h7xx_hal::{pac, prelude::*};
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use cortex_m_log::println;
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use cortex_m_log::{
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destination::Itm, printer::itm::InterruptSync as InterruptSyncItm,
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};
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#[entry]
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fn main() -> ! {
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let cp = cortex_m::Peripherals::take().unwrap();
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let dp = pac::Peripherals::take().unwrap();
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let mut log = InterruptSyncItm::new(Itm::new(cp.ITM));
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// Constrain and Freeze power
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println!(log, "Setup PWR... ");
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let pwr = dp.PWR.constrain();
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let vos = pwr.freeze();
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// Constrain and Freeze clock
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println!(log, "Setup RCC... ");
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let rcc = dp.RCC.constrain();
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let ccdr = rcc.sys_ck(100.mhz()).freeze(vos, &dp.SYSCFG);
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println!(log, "");
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println!(log, "stm32h7xx-hal example - Blinky");
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println!(log, "");
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
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// Configure PE1 as output.
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let mut green = gpiob.pb0.into_push_pull_output();
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let mut yellow = gpioe.pe1.into_push_pull_output();
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let mut red = gpiob.pb14.into_push_pull_output();
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// Get the delay provider.
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let mut delay = cp.SYST.delay(ccdr.clocks);
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let mut num = 0;
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loop {
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delay.delay_ms(500_u16);
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if num & 4 != 0 {
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green.set_high().unwrap();
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}
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else {
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green.set_low().unwrap();
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}
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if num & 2 != 0 {
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yellow.set_high().unwrap();
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}
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else {
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yellow.set_low().unwrap();
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}
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if num & 1 != 0 {
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red.set_high().unwrap();
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}
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else {
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red.set_low().unwrap();
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}
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num = (num + 1) % 8;
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}
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}
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@ -0,0 +1,62 @@
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#![no_std]
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use stm32h7xx_hal::{
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hal::{
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digital::v2::{
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InputPin,
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OutputPin,
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},
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blocking::spi::Transfer,
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},
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pac,
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prelude::*,
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spi,
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};
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use cortex_m;
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use cortex_m::asm::nop;
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use cortex_m_semihosting::hprintln;
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use nb::block;
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/*
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* Basic structure for CPLD signal multiplexing
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*/
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pub struct CPLD<SPI, CS0, CS1, CS2> {
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spi: SPI,
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chip_select: (CS0, CS1, CS2),
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}
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impl<SPI, CS0, CS1, CS2> CPLD<SPI, CS0, CS1, CS2> where
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SPI: Transfer<u8>,
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CS0: OutputPin,
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CS1: OutputPin,
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CS2: OutputPin,
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{
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// Constructor for CPLD
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pub fn new(spi: SPI, chip_select: (CS0, CS1, CS2)) -> Self {
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// Init CS to be 0
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let mut obj = Self{spi, chip_select};
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obj.select_chip(0);
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return obj
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}
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// Select chip
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pub fn select_chip(&mut self, channel: u8) {
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match channel & (1 << 0) {
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0 => self.chip_select.0.set_low(),
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_ => self.chip_select.0.set_high(),
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};
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match channel & (1 << 1) {
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0 => self.chip_select.1.set_low(),
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_ => self.chip_select.1.set_high(),
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};
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match channel & (1 << 2) {
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0 => self.chip_select.2.set_low(),
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_ => self.chip_select.2.set_high(),
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};
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}
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}
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26
src/main.rs
26
src/main.rs
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use core::ptr;
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use nb::block;
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mod cpld;
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#[entry]
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fn main() -> ! {
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@ -37,6 +38,7 @@ fn main() -> ! {
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let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
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let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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@ -71,20 +73,18 @@ fn main() -> ! {
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let mut data :u8 = 0xAD;
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let mut switch = cpld::CPLD::new(spi, (
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gpiob.pb12.into_push_pull_output(),
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gpioa.pa15.into_push_pull_output(),
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gpioc.pc7.into_push_pull_output(),
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));
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loop {
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hprintln!("Sent {}", data).unwrap();
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block!(spi.send(data)).unwrap();
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data = block!(spi.read()).unwrap();
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hprintln!("Read {}", data).unwrap();
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// hprintln!("Sent {}", data).unwrap();
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// block!(spi.send(data)).unwrap();
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// data = block!(spi.read()).unwrap();
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// hprintln!("Read {}", data).unwrap();
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nop();
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}
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}
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